Error using SystemVerilog interfaces and iverilog

Question

I am trying to write a testbench for a simple PISO register design. In the testbench and design, I am using an interface to encapsulate all the signals to and from the design (with modport for TB and DUT). But, when I compile it with icarus-verilog, I get these errors:

iverilog -g2012 piso_tb.sv
./piso.sv:25: syntax error
./piso.sv:1: Errors in port declarations.
piso_tb.sv:9: syntax error
piso_tb.sv:9: error: Invalid module instantiation

I tried changing the flag to -g2005-sv, but it gives the same error. Here are my design and TB files:

piso.sv : Design + Interface

interface my_piso;

    logic [7:0] din;
    logic resetn;
    logic dout;
    logic din_en;

    modport TB (
        output din,
        output resetn,
        input dout,
        output din_en
    );

    modport DUT (
        input din,
        input resetn,
        input din_en,
        output dout
    );

endinterface


module model (input clk, my_piso piso_if);
  reg [7:0] temp;

  always @(posedge clk) begin
    if(!piso_if.resetn) begin
      temp <= 0;
    end else begin
      if(piso_if.din_en) begin
        temp <= piso_if.din;
      end else begin
        temp <= temp >> 1;
      end
    end
  end

  assign piso_if.dout = temp & 1'b1;

endmodule

---

piso_tb.sv : Testbench

`include "piso.sv"

module model_tb;

    reg clk;

    always #5 clk = ~clk;

    my_piso piso_if;

    model dut(
        .clk(clk),
        .piso_if(piso_if.DUT)
    );

    initial begin
        $dumpfile("model.vcd");
        $dumpvars;
    end

    initial begin
        $display("time\tclk\tresetn\tdin_en\tdin\tdout");
        $monitor("%d\t%b\t%b\t%b\t%b\t%b", $time, clk, piso_if.resetn, piso_if.din_en, piso_if.din, piso_if.dout);
    end

    initial begin
        clk <= 0;
        piso_if.resetn <= 0;
        piso_if.din_en <= 0;
        piso_if.din <= 0;

        @(posedge clk);

        piso_if.resetn <= 1;
        piso_if.din_en <= 1;
        piso_if.din <= $random;

        @(posedge clk);

        repeat(10) begin
            piso_if.din_en <= 0;
            @(posedge clk);
        end

        $finish;
    end
endmodule

I also tried shifting the interface code into a separate file, but it gives the same error. Is there any syntax error that I am committing? What's the problem?

Answer 1

The testbench module has a syntax error. When instantiating an interface, it is required to have a port list after the instance name, just like with module instances.

Change:

my_piso piso_if;

to:

my_piso piso_if ();

It is legal for the port list to be empty.

---

However, this does not fix the other iverilog syntax errors you are seeing. iverilog does not support many SystemVerilog features. If you want to use this syntax, you need to either try updating iverilog to a newer version, or use another simulator. There are other simulators on the EDAPlayground site. For example, the code runs on the Cadence simulator there.