How to use ripple adder for addition in shift and add binary Multiplier?

Question

module bin_mult(
    output reg [7:0]mult,
    output reg [1:0]count,
    output carry,
    input [3:0]a,b,
    input clk,load);

    reg enable;
    reg [7:0]sum;
    reg [3:0]m[3:0];
    //reg [1:0]count;
    integer i,j;

    always@(*) begin
        for(i=0;i<=3;i=i+1) begin
            for(j=0;j<=3;j=j+1) begin
                m[i][j]=b[i]&a[j];
            end
        end
    end

    ripple_add ADD(sum,carry,({4'd0,m[count+1]}<<(count+1)),mult,enable);

    always@(posedge clk) begin
        if(load) begin
            mult<={4'd0,m[0]};
            count<=0;
        end
        else if(count==3) count<=0;
        else begin
            count<=count+1;
            if(b[count+1]) begin
                //mult<=({4'd0,m[count+1]}<<(count+1))+mult;
                enable<=1'b1;
                mult<=sum;
            end
            else mult<=mult;
        end
    end
endmodule

module ripple_add(
    output [7:0]sum,
    output co,
    input [7:0]a,b,
    input en);

    parameter cin=1'b0;
    genvar i;
    wire [7:0]w;
    reg [7:0]A,B;

    always@(*) begin
        if(en) begin
            A=a;
            B=b;
        end
        else {A,B}=0;
    end

    full_add FA0(sum[0],w[0],A[0],B[0],cin);
    generate for(i=1;i<=7;i=i+1)
    begin
        full_add FA(sum[i],w[i],A[i],B[i],w[i-1]);
    end
    endgenerate
    assign co=w[7];
endmodule

module full_add(
    output s,co,
    input af,bf,cin);
    assign s=af^bf^cin;
    assign co=(af&bf)|(bf&cin)|(af&cin);
endmodule

I have written Verilog code for shift and add binary multiplier. In the above code, I tried to use ripple carry adder for performing addition (mult<=({4'd0,m[count+1]}<<(count+1))+mult), but I'm getting the following errors:

test.v:22: error: reg sum; cannot be driven by primitives or continuous assignment.

test.v:22: error: Output port expression must support continuous assignment.

test.v:22:      : Port 1 (sum) of ripple_add is connected to sum.

Is there any alternate solution?

Answer 1

I get these errors when I compile the code with iverilog. The code compiles without errors when I use the -g2012 option:

iverilog -g2012 test.v

g2012 enables the IEEE1800-2012 standard, which includes SystemVerilog.

To get help on the iverilog command, use the -h option:

iverilog -h