systemverilog assertion become vacuous match when it has if...else statement

Question

I met an vacuous match issue. When the if condition is false, code will go to else statement. But I don't know why it is vacuous match. Code as below:

property wr_cmd_will_set_busy ;

    @(negedge pclkdbg) disable iff(rst_a  )
    ( apb_new_trans  && (paddr_dm == ADDR_ABS_COMM) && (pwrite_dm) ) |-> 
    if(pwdata_dm[17])
        ##[0:1] $rose(abs_stat_busy)
    else
        $stable(abs_stat_busy)[*3] ; 

endproperty

the waveform is here. enter image description here I am doubting that if I cannot use if...else statement here. Thanks