How do I fix error in vs code: " Wrong number of ports. Expecting 8, got 7."

Question

I'm trying to make a 1:4 Demultiplexer but I keep getting the error about my ports. Every time I try and type the command

iverilog -o Lab12_tb.vvp Lab12_tb.v

to simulate my text bench in the vs code terminal, it pop up the error.

Design

module Lab12 (
   W,X,Y,Z, Cin, A, B,
);

input Cin,A,B;
output W,X,Y,Z;

assign W = (Cin) & (~A) & (~B);
assign X = (Cin) & (A) & (~B);
assign Y = (Cin) & (~A) & (B);
assign Z = (Cin) & (A) & (B);

endmodule

Testbench

// Testbench for 1:4 Demultiplexer
`timescale 1ns/1ns
`include "Lab12.v"

module Lab12_tb;

reg Cin,A,B;
wire  W,X,Y,Z;

Lab12 uut (Cin, A, B, W, X, Y, Z);

//iverilog -o Lab12_tb.vvp Lab12_tb.v

initial begin
  $dumpfile("Lab12_tb.vcd");
  $dumpvars(0,Lab12_tb);

   Cin = 1; A = 0; B = 0;                                     
   #1 
   Cin = 1; A = 1; B = 0; 
   #1 
   Cin = 1; A = 0; B = 1;
   #1 
   Cin = 1; A = 1; B = 1; 

  $finish();
  $display("Completed");
end

initial begin
  $monitor("%t| Cin = %d| A = %d| B = %d| W = %d| X = %d| Y = %d| Z = %d", 
  $time, Cin,A,B, W,X,Y,Z); 
end


endmodule

Answer 1

There are five issues total, the first 3 cause errors, the last two are behavioral.

1. As pointed out in the comments by @Markus Safar, there is an extra comma at the end of the testbench dut instance association list. It makes the tool think there is another port expected there. The correction is obliviously to use (Cin, A, B, W, X, Y, Z);

2. The 2nd is that you are relying on positional association for the port list, and the ports are out of order WRT the testbench variables. The order in your module is this W,X,Y,Z, Cin, A, B the order in the testbench is this Cin, A, B, W, X, Y, Z. The module W port is getting associated with the testbench reg variable Cin and so on. The module drives W and the testbench drives Cin, so the compiler flags this as multiple drivers and produces an error. Same with module port X and testbench variable reg A, and so on for each driving variable in the testbench.

The best practice to avoid this is to use named association for the port map list, so that the order does not matter. This sample of testbench code fixes both errors. The .<variable name> specifies the module port name, the parenthesis contain the local testbench variable name. In your case the names should match.

Using a vertical style makes it easier to view and maintain without making mistakes.

// --- Make this change in the testbench ---
// Don't use positional association, its too easy to make a mistake
// Lab12 uut (Cin, A, B, W, X, Y, Z);

// Use named association for mapping module ports to testbench variables
  Lab12 uut (
    .Cin(Cin),
    .A(A),
    .B(B),
    .W(W),
    .X(X),
    .Y(Y),
    .Z(Z)
    );

3. I think some junk ended up in your post at the end of the $finish line 'your text' Just remove this because it causes an error.

4. You have these two lines at the end of your testbench initial block

$finish(); `your text`
$display("Completed");

The $finish will cause the simulation to stop and the $display will not execute. Swap the order so that "Completed" is printed.

$display("Completed");
$finish();

Note that I also removed the junk text.

5. Recommend adding a #1 delay at the end of your vectors so that you can observe the final output in the waves display. Otherwise the last stimulus vector and $finish are applied at the same time, and will you not be able to see the output result. Recommend changing the end of the vector generation process to:

initial begin
  // ... other statements ...
  #1;
  Cin = 1; A = 1; B = 1; 
  // adding delay after stimulus
  #1;
  $display("Completed");
  $finish();
end