i am trying to implement a rtl code where i am giving 1 bit reg data type to an 4 bit reg data type under always block.
lets say X & Y are two reg data type.where X is 4 bit reg data type and Y is 1 bit reg data type.
module rtL
reg [3:0]X;
reg Y;
always@(posedge clk)begin
X<=Y;
end
It’s always ok to make assignments from smaller to larger width signals. Unsigned types get 0 extended and signed types get sign extended.
Going from larger to smaller widths get truncated, which is OK in Verilog simulation, but other tools may issue warnings.