4-bit ALU SLT operation

Question

I don't understand how to create the SLT instruction inside my 4-bit ripple ALU, that consists of 1-bit ALU's. I don't know what to put in the 2'b11 for the 1-bit ALU and how to connect them together in my 4-Bit ALU. How would I set the LSB if I can't tell whether or not a < b till the MSB ALU. Here's my code, any help at all would be appreciated.

Full Adder:

module FullAdder(a, b, cin, sum, cout);
  input a, b, cin;
  output sum, cout;
  
  assign sum = a ^ b ^ cin;
  assign cout = (a & b) | ((a ^ b) & cin);
endmodule

1-Bit ALU:

module OneBitALU(a, b, cin, ainv, binv, less, op, result,
cout, set);
  input a, b, cin;
  input ainv, binv;
  input less;
  input [1:0] op;
  
  output result;
  output cout;
  output set;
  wire aneg, bneg;
  
  reg result;  
  reg tmp;
  reg set;
  assign aneg = ainv ? ~a : a;
  assign bneg = binv ? ~b : b;
  
  FullAdder fulladder(aneg, bneg, cin, tmp, cout);
  
  always @ (*) begin
    case(op)
      2'b00: result = aneg & bneg;
      2'b01: result = aneg | bneg;
      2'b10: result = tmp;
      2'b11: result = less;
      default: result = 1'b0;   
    endcase
  end
endmodule
    

4-bit ALU:

module FourBitALU(a, b, op, result, cout);
  input [3:0] a, b; 
  input [3:0] op;
  
  output [3:0] result;
  output cout;
  reg [3:0] result;
  reg [3:0] sum;
  wire [2:0] co;
  
  OneBitALU oba0(a[0], b[0], op[2], op[3], op[2], sum[3], op[1:0], result[0], co[0], sum[0]);
  OneBitALU oba1(a[1], b[1], co[0], op[3], op[2], 0, op[1:0], result[1], co[1], sum[1]);
  OneBitALU oba2(a[2], b[2], co[1], op[3], op[2], 0, op[1:0], result[2], co[2], sum[2]);
  OneBitALU oba3(a[3], b[3], co[2], op[3], op[2], 0, op[1:0], result[3], cout, sum[3]);
  
endmodule

Changed it so when op = 0111 then result is set to less, but now I only ever get a high impedance state.

Answer 1

For the SLT (set less than) instruction, according to the RISC-V instruction set architecture it should be implemented as the following: " Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd."

so review the ISA you tring to implement to know the correct way of implementing it. if your ISA is similar to RISC-v, you should correct your 1- bit ALU to be:

module OneBitALU(a, b, cin, ainv, binv, less, op, result,
cout, set);
  input a, b, cin;
  input ainv, binv;
  input less;
  input [1:0] op;
  
  output result;
  output cout;
  output set;
  wire aneg, bneg;
  
  reg result;  
  reg tmp;
  reg set;
  assign aneg = ainv ? ~a : a;
  assign bneg = binv ? ~b : b;
  assign less = (a>b)? 1'b1: 1'b0 ; // new line
  FullAdder fulladder(aneg, bneg, cin, tmp, cout);
  
  always @ (*) begin
    case(op)
      2'b00: result = aneg & bneg;
      2'b01: result = aneg | bneg;
      2'b10: result = tmp;
      2'b11: result = less;
      default: result = 1'b0;   
    endcase
  end
endmodule

Answer 2

IMHO: Abdelhady's solution scales better, but may raise an eyebrow if you have to keep everything in boolean logic. If there is want for a 1 bit solution and keep things as binary operations then let's start by looking at the truth table.

The truth table for an SLT 1 bit operation is:

A,B, SLT(aka. A<B)
------------
0 0    0
0 1    1
1 0    0
1 1    0

Since it's so specific you could forgo the less than statement as suggested in Abdelhady's solution and use the following

...
assign less =  ~a & b
...

When looking at a boolean expression for 4 bits, since it's a ripple ALU, you should be set. If you have to code a non-ripple version then you may want to consider a 4 bit comparator. A better description of what that boolean expression looks like for a 4 bit comparitor can be found here: https://www.electronicshub.org/digital-comparator-and-magnitude-comparator/