Error message coming up when compiling iVerilog Code

Question

I am receiving the following error codes in my output. I am using Icarus Verilog, with VSCode as my IDE. Would anyone know how to resolve this?

No top level modules, and no -s option.

This issue has occurred in one other instance before and I was not sure how to proceed.

    `timescale 1ns / 1ps

     // Definition of the 8-bit combinational shifter module
     module combinational_shifter(
    input [7:0] A,
    input [3:0] n,
    input dir,
    output reg [7:0] Y
);

     always @(*) begin
    if (dir == 1'b0) // If dir is 0, shift to the right
        Y = A >> n;
    else // Otherwise, shift to the left
        Y = A << n;
     end

    endmodule

     // Testbench module for the combinational shifter
     module combinational_shifter_tb;

     // Inputs to the shifter
     reg [7:0] A;
     reg [3:0] n;
     reg dir;

      // Output from the shifter
       wire [7:0] Y;

      // Instantiate the Unit Under Test (UUT)
     combinational_shifter uut (
    .A(A), 
    .n(n), 
    .dir(dir), 
    .Y(Y)
     );

     initial begin
    // Initialize Inputs
    A = 8'b10101010; // Example input to test
    dir = 0; // Start with right shift
    n = 0;
    
    // Test all possible shifts
    for (n = 0; n < 16; n = n + 1) begin
        #10; // Delay to observe changes
        $display("Right Shift: A = %b, n = %d, Result = %b", A, n, Y);
    end
    
    dir = 1; // Change to left shift
    for (n = 0; n < 16; n = n + 1) begin
        #10; // Delay to observe changes
        $display("Left Shift: A = %b, n = %d, Result = %b", A, n, Y);
    end
    end

   endmodule