4-bit register always shows output 0

Question

module register(input [7:0] inp, input load,clk,clr, output reg [7:0] out);

always@(posedge clk or posedge clr) begin
    if(clr)
        out <= 8'b00000000;
    else if(load)
        out<= inp;
        
end

endmodule

module register_tb;

reg [7:0] inp;
reg load,clk,clr;
wire [7:0] out;
integer count1,count2;

register store(inp,load,clk,clr,out);

initial begin
    clk = 1'b0;
    repeat(2**10) #10 clk = {$random};
end

initial begin
    for(count1 = 0;count1<2**8;count1 = count1 + 1) begin
        for(count2 = 0;count2<4;count2 = count2 + 1) begin
            {clr,load} = count2;
            {inp} = count1;
            #10;
        end
    end
end

endmodule

I am trying to make a 4-bit register, but I am stuck at this error. I am not able to understand why my code always outputs zero. I tried debugging it, but I could not find the error.

Answer 1

As your waveforms show, out is not 0 at all times; it does change value.

You design code looks fine, but your testbench code does not follow good practices for synchronous logic. This is why you get a strange looking out waveform.

I recommend using a clock signal with 50% duty cycle and driving all other inputs from the clock using nonblocking assignments as follows:

module register_tb;

reg [7:0] inp;
reg load,clk,clr;
wire [7:0] out;
integer count1,count2;

register store(inp,load,clk,clr,out);

initial begin
    clk = 1'b0;
    forever #10 clk = ~clk;
end

initial begin
    clr = 1;
    load = 0;
    inp = 5;
    repeat (2) @(posedge clk);
    clr <= 0;
    repeat (2) @(posedge clk);
    load <= 1;
    repeat (1) @(posedge clk);
    load <= 0;
    repeat (5) @(posedge clk);
    $finish;
end

endmodule

Waves:

You can clearly see out change from 0 to 5.