Why does my four bit multiplier enter infinite loop when testbenching it?

Question

My four bit multiplier described in the code below enters an infinite loop when I try to test it via a simulation in Vivado 2022.2. The implementation of the multiplier is "Shift-and-Add Multiplication". The test bench vhdl code is written correctly.

When I cancel the simulation, the application allows me to step in like a debugger, and it seems like the "while" loop runs infinitely, because N is not decremented. I searched for answers and I also added the sensitivity list, and it still shows the same problem.

Do you have any ideas as to why the while does not stop and N is not decremented? Or if it is any other problem somewhere else?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity four_bit_multiplier is
  Port ( x : in STD_LOGIC_VECTOR(3 downto 0);
         y : in STD_LOGIC_VECTOR(3 downto 0);
         result : out STD_LOGIC_VECTOR(7 downto 0) );
end four_bit_multiplier;

architecture Behavioral of four_bit_multiplier is

component eight_bit_adder is
  Port (x : in STD_LOGIC_VECTOR(7 downto 0);
        y : in STD_LOGIC_VECTOR(7 downto 0);
        c_in: in STD_LOGIC;
        c_out: out STD_LOGIC;
        sum : out STD_LOGIC_VECTOR(7 downto 0) );
end component;


signal B : STD_LOGIC_VECTOR(7 downto 0);
signal Q : STD_LOGIC_VECTOR(7 downto 0);
signal A : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal adder_out : STD_LOGIC_VECTOR(7 downto 0);
signal c_out : STD_LOGIC;
signal N: integer := 4;

begin

p1: eight_bit_adder port map(B, A, '0', c_out, adder_out);

process(x, y, B, N, Q, adder_out)
begin

B <= "0000" & x;
Q <= "0000" & y;

while N > 0 loop
    if Q(0) = '1' then
        A <= adder_out;
    end if;
    
    B <= B(6 downto 0) & '0';
    Q <= '0' & Q(7 downto 1);
    N <= N - 1;
end loop;

result <= A;

end process;

end Behavioral;

Answer 1

Remember that VHDL is a description language, not a programming language. It includes such features, though, but only for simulation.

Loops with while are generally not synthesizable. Instead, use a for loop.

Answer 2

The issue here is that you have used a signal, when instead you should have used a variable. Because Signals only get updated when a process syspends, the signal N is never updated, and with an initial value of 4 it never goes to any other value. This will mean the condition:

while N > 0 loop

will always be true, because the value of N can never be updated to 3 via

N <= N-1;

There are other issues, all related to using signals and loops. If you fix the N problem, you will still have problems assigning multiple values to various signals, with each assignment simply overriding the previous assignment.

As @thebusybee points out, While loops in VHDL are generally not synthesisable. The code presented appears to be trying to write VHDL as a software programming language.