For a multi-file Verilog project using Yosys for synthesis, the script would generally look something like the following:
# read the all files
read_verilog *.v
# synthesis
synth -top
# output the synthesis result
write_verilog res.v
If a file is modified, the script must be rerun, triggering the synthesis of all files. This process becomes time-consuming, especially for larger projects. Does Yosys offer any methods to support incremental synthesis, allowing re-synthesis only for the modified file? If so, could you please provide specific script details with examples? In other words, suppose there are three files. For the initial synthesis, all three files are synthesized. If we later modify one file, how can Yosys be used to synthesize only the modified files?
If Yosys does not support incremental logic synthesis, are there other tools that can accomplish this?
In the scenario where module m1 instantiates m2 (located in different files), if modifications are made to m2, is it correct to infer that both m1 and m2 would need to undergo re-synthesis?
Does the outcome of logic synthesis will eventually yield a singular netlist file?
Incremental synthesis works by synthesizing each module separately in the first run and in case of modification (subsequent runs), only the modified modules are synthesized. During incremental synthesis, each module is synthesized to create netlist and then all the netlist are assemble to make one final netlist i.e. the final synthesized design.
But, Yosys doesn't have built-in support for incremental logic synthesis and if any file is modified, the entire synthesis process needs to be rerun. Alternatively, you can use custom scripts (such as Git with make file) to determine which files have been modified and selectively rerun synthesis only for those files.