Parameterizable FIFO with multiple inputs and outputs?

Question

I want to create a FIFO with multiple & parameterizable number of inputs and outputs. Saying as soon as there are enough data, the FIFO will pump them out. In my use case, I have 4 inputs and outputs, something like this:

input  [7:0] din1, din2, din3, din4;
input  [3:0] din_valid;
output [7:0] dout1, dout2, dout3, dout4;
output       dout_valid;

With examples:

din*       = 0,1,2,3 -> 4,5,6,7 -> 8,9,0,1
din_valid  = 4'b0011 -> 4'b1101 -> 4'b1110
dout       = x,x,x,x -> x,x,x,x -> 2,3,4,5 -> 7,8,9,0 -> x,x,x,x
dout_valid = 1'b0    -> 1'b0    -> 1'b1    -> 1'b1    -> 1'b0

I have been able to make this working by having like a fixed size memory registers, and shifting the data in manually with case statements for din_valid (0000, 0001, etc.).

However, this seems to be very inefficient if the number of outputs increases, to like 6 or 8. I can have a read & write pointers as in normal FIFO to traverse the memory accordingly; however, the problem arises when the value of read & write pointers overflow, and additional "wrapping around" logic is super complicated since we are not increasing them by just 1.

Are there any other methods to create a multi-input, multi-output FIFO, with the "memory shifting" logic being parameterizable (in this case we will just make din1, din2... a single [NUM_INPUTxBIT-1:0]din) ? Any help is greatly appreciated.

Answer 1

Are there any other methods to create a multi-input, multi-output FIFO, being parameterizable ... ?

Yes, you can use unpacked array ports as well:

module fifo #(parameter N=4) (
    input  [N-1:0] din_valid,
    input  [7:0]   din  [N],
    output [7:0]   dout [N]
);

endmodule

Refer to IEEE Std 1800-2017, section 7.4.2 Unpacked arrays.