Xilinx Vivado schematic for if else statements

Question

I am learning SystemVerilog. While coding, the synthesis schematic for the following if statements don't make sense to me.

module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
    );
    
    always @*
    begin
        dout = 0;
        
      priority  if(sela)
            dout = da;
        if(selb)
            dout = db;
        if(selc)
            dout = dc;

        
    end
    
endmodule

Here is the synthesized schematic:

How to understand the schematic when sela is not used? I am also not able to make sense of S=default value on the muxes.

Here is the message generated by Vivado. There are no errors or warnings during the synthesis.

[Synth 8-293] found qualifier priority on case statement: implementing as full_case ["C:/Users/homealien/Xilinx/ifelse-test/ifelse-test.srcs/sources_1/new/ifelseDUT.sv":32]

Answer 1

Because your priority if statement does not contain an else clause, synthesis is treating it as:

if(sela)
   dout = da;
else
   dout = 'x; // don't care

and that is being optimized as just

dout = da;

This is because the priority is an assumption/assertion that a conditional branch will always be taken. Without an else clause, synthesis is generating logic assuming the condition is always true. This should have been caught as a synthesis error, but it is a legal description.

What you probably intended is:

always_comb
      priority if(sela)
            dout = da;
      else if(selb)
            dout = db;
      else if(selc)
            dout = dc;
      else
            dout = 0;

Now you have written the code is such a way that a conditional branch statement will always be taken under all possible conditions.

Answer 2

Refer to IEEE Std 1800-2017, section 12.4.2 unique-if, unique0-if, and priority-if

If the keywords unique or priority are used, a violation report shall be issued if no condition matches unless there is an explicit else.

Since you have no else with the priority if, the Cadence simulator generates a warning. Perhaps the Vivado simulator did as well. Check your log files.

You likely want an if/else statement rather than 3 separate if statements:

module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
    );
    
    always @*
    begin
        dout = 0;
        if (sela) begin
            dout = da;
        end else if (selb) begin
            dout = db;
        end else if (selc) begin
            dout = dc;
        end
    end
    
endmodule

Your problematic Verilog code results in a schematic with problems.

This Verilog code should fix the schematic problems.

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I am also not able to make sense of S=default value on the muxes.

To find out what S=default means on the schematic, read the Vivado documentation, contact Vivado for support or ask on a Vivado forum.