RISVC Single Cycle Processor Data Path and Testbench

Question

I have all the control signals as inputs. I cannot seem to connect everything correctly. I need my wave configuration to look like the reference waveform, but somehow my waveform ends up with everything X and Z. How do I fix this?

My waveform:

Reference Waveform:

RISC Architecture:

The parameters and input and outputs were given and not to be edited with, so I didn't include them.

wire [7:0] d;
wire [7:0] q; 
wire [7:2] PC;
wire [7:0] PCPlus4;
wire MemRead;            
wire MemWrite;           
wire [8:2] addr;         
wire [31:0] write_data;  
wire [31:0] read_data;   
wire [31:0] instruction;
wire [4:0] rg_rd_addr1, rg_rd_addr2, rg_wrt_addr;
wire Sel;  
wire [31:0] D1;      
wire [31:0] D2;     
wire [31:0] Y; 
wire [31:0] A_in;    
wire [31:0] B_in;   
wire [3:0] ALU_Sel;   
wire [31:0] ALU_Out;  
wire Carry_Out;        
wire Zero;             
wire Overflow;       
wire [31:0] WriteBack_Data;
wire [31:0] InstCode;    // Instruction input to ImmGen
wire [31:0] ImmOut; 

FlipFlop flipflop_instance (
    .d(PCPlus4),
    .clk(clk),
    .reset(reset),
    .q(PC)
);

InstMem instruction_memory (
    .addr(PC[9:4]),      
    .instruction(instruction)
);

assign rg_rd_addr1 = instruction[19:15];
assign rg_rd_addr2 = instruction[24:20];
assign rg_wrt_addr = instruction[11:7];

assign opcode = instruction[6:0];
assign funct3 = instruction[14:12];
assign funct7 = instruction[31:25];

// Instantiate RegFile
RegFile reg_file (
    .clk(clk),
    .reset(reset),
    .rg_wrt_en(reg_write),
    .rg_rd_addr1(instruction[19:15]),
    .rg_rd_addr2(instruction[24:20]),
    .rg_wrt_addr(instruction[11:7]),
    .rg_rd_data1(Reg1),
    .rg_rd_data2(Reg2)
);

ImmGen immediate_generator (
    .InstCode(InstCode),
    .ImmOut(ExImm)
);

Mux_32_To_1 mux_1 (
    .S(alu_src),
    .D1(Reg2),
    .D2(ExtImm),
    .Y(SrcB)
);

alu_32 my_alu (
    .A_in(Reg1),
    .B_in(SrcB), 
    .ALU_Sel(ALU_Sel), 
    .ALU_Out(alu_result), 
    .Carry_Out(Carry_Out),
    .Zero(Zero),      
    .Overflow(OverFlow) 
);

DataMem data_memory (
    .MemRead(mem_read),
    .MemWrite(mem_write),
    .addr(alu_result),
    .write_data(write_data),
    .read_data(D2)
);
Mux_32_To_1 mux_2 (
    .S(mem2reg),
    .D1(Reg2),
    .D2(ExtImm),
    .Y(WriteBack_Data)
);

endmodule 

Answer 1

There are a couple of issues.

1. You have not instantiated the Adder in your provided code. Adder module should derive PCPlus4 that is being fed to FlipFlop. You are seeing all X because PCPlus4 is not begin driven by any logic that generates X at the output of flipflop and then these Xs propagate throughout .

2. reg_write is not being driven. It should come from the test bench. Similarly there are more signals coming from testbench. Pl provide your test bench for further clarification.