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20 TechQA 2024-03-29T16:42:00.950000How to connect combo code to a module's interface modport?
49 views
Asked by DarinT
Xilinx Vivado schematic for if else statements
98 views
Asked by tulamba
Incremental synthesis with yosys
88 views
Asked by Echo_Zero
Why does running Synthesis take the same amount of time every time with Quartus, Vivado and Libero?
99 views
Asked by gyuunyuu
Yosys: how to convert D-latches to FFs and LUTs?
34 views
Asked by AlfaRossati
2d array structure flattened into registers?
32 views
Asked by Makuta Arguilleres
When designing digital circuits, which is more power efficient, an if-statement or a multiplication (particular case)?
88 views
Asked by Julián Andrés Hernández Potes
Synthesis error in Vivado: [Synth 8-3380] loop condition does not converge after 2000 iterations
80 views
Asked by Kamran Khan
Parameterizable FIFO with multiple inputs and outputs?
153 views
Asked by Ratiasu
Post-synthesis simulation error: unable to find ports due to flattening 2D array ports to 1D
139 views
Asked by Farah Bayomi
What is the basis for setting parameter values in the sdc file?
143 views
Asked by benjstark
How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?
270 views
Asked by Xiuhua Yang
How to know whether a Verilog code can be synthesized?
115 views
Asked by benjstark
Vivado won't synthesize BRAM, making LUT instead
217 views
Asked by dduy_le
Vivado linter: inferred latch for signal 'out_reg'
231 views
Asked by bruin
Flip flop reset with ternary operator instead of if-else statement
144 views
Asked by Mahmoud Maarouf
Setting values in an initial block in Verilog
351 views
Asked by Didier Malenfant
Can synthesizers pay attention to intentional 'Z' at compile time?
114 views
Asked by James Strieter
How to make the data_flow control of a matrix multiplier synthesizable?
206 views
Asked by engineer1155