List Question
20 TechQA 2024-03-30T16:17:59.480000Formal verification of state machine with SymbiYosys not giving expected results
102 views
Asked by Christopher P
Verilog: mapping an memory array
89 views
Asked by Filip
Incremental synthesis with yosys
88 views
Asked by Echo_Zero
Yosys: how to convert D-latches to FFs and LUTs?
34 views
Asked by AlfaRossati
Verilog/SystemVerilog: "constant" function is considered non-constant
384 views
Asked by em-rg-ncy
Can I use yosys in Visual Studio Code with connect to WSL
105 views
Asked by viên phùng
yosys: Generate Graphviz representation of design without running 'hierarchy'
208 views
Asked by bagelfire
sequential RTL to combinational gate netlist
53 views
Asked by gizen
Yosys optimizes GPIO RX module away
157 views
Asked by Cornelius Korinthia
Getting "Warning: Driver-driver conflict" errors from yosys
197 views
Asked by Justin808
Yosys: how to remove useless internal wires
188 views
Asked by alex137
BLIF outputed by yosys involves DFF, and the BLIF file cannot be read by ABC
296 views
Asked by Pu Yuan
Logical synthesis of decoder into standard logical cells
141 views
Asked by gudise
Yosys: Multiple edge sensitivities for asynchronous reset
692 views
Asked by Neekon Saadat
Support for ICE40UP5K-SG48I?
384 views
Asked by TomP
What is the most powerful FPGA that yosys / Project IceStorm will target?
896 views
Asked by Daniel
Does operator of `[]` of std::map always put the new item into the first place of iterator?
123 views
Asked by Shore
why are SB_LUT4 and SB_DFF not being packed by nextpnr?
163 views
Asked by Hammdist
Why do I get "Module port is neither input nor output" for all wires?
240 views
Asked by Ghosty Toasty