yosys: Generate Graphviz representation of design without running 'hierarchy'

Question

I am using yosys to read a gate-level Verilog file, and subsequently output the design to a Graphviz dot file to visualize it. Measuring the time taken for the yosys commands used, it seems like parsing to an AST is much faster than generating the hierarchy.

For example, using a small 9.3MB Verilog design file,

1. 'read_verilog -defer' takes 465ms
2. 'hierarchy -auto-top' takes 42,961ms

For a larger, real-world design that I tried, the 'hierarchy' command does not end even after about 2 hours.

My question is, is it possible to output a Graphviz representation without running the 'hierarchy' command? I tried exploring the options of 'read_verilog' and 'hierarchy' to exclude unneeded operations, but cannot seem to find one that speeds up the 'hierarchy' command.

Here is my Tcl script:

# source file
set time_parse_start [clock clicks -milliseconds]
yosys read_verilog -defer $::env(YOSYS_INPUT_VERILOG)
set time_taken [expr [clock clicks -milliseconds] - $time_parse_start]
puts "Time taken to parse: $time_taken ms"

set time_hier_start [clock clicks -milliseconds]
yosys hierarchy -auto-top
set time_taken [expr [clock clicks -milliseconds] - $time_hier_start]
puts "Time taken to derive hierarchy: $time_taken ms"

set time_output_start [clock clicks -milliseconds]
yosys show -viewer none -format dot -prefix $::env(YOSYS_OUTPUT_DOTPREFIX)
set time_taken [expr [clock clicks -milliseconds] - $time_output_start]
set total_time_taken [expr [clock clicks -milliseconds] - $time_parse_start]
puts "Time taken to output .dot file: $time_taken ms"
puts "Total time taken: $total_time_taken ms"

Executed with: YOSYS_INPUT_VERILOG=c10_default.vqm YOSYS_OUTPUT_DOTPREFIX=c10_default yosys test.tcl

Output:

 Yosys 0.34 (git sha1 4a1b5599258, clang 14.0.0 -fPIC -Os)

1. Executing Verilog-2005 frontend: c10_default.vqm
Parsing Verilog input from `c10_default.vqm' to AST representation.
Storing AST representation for module `$abstract\eight_bit_uc'.
Successfully finished Verilog frontend.
Time taken to parse: 507 ms

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Finding top of design hierarchy..
root of   0 design levels: $abstract\eight_bit_uc
Automatically selected $abstract\eight_bit_uc as design top module.

2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\eight_bit_uc'.
Generating RTLIL representation for module `\eight_bit_uc'.

2.3. Analyzing design hierarchy..
Top module:  \eight_bit_uc

2.4. Analyzing design hierarchy..
Top module:  \eight_bit_uc
Removing unused module `$abstract\eight_bit_uc'.
Removed 1 unused modules.
Time taken to derive hierarchy: 44377 ms

3. Generating Graphviz representation of design.
Writing dot description to `c10_default.dot'.
Dumping module eight_bit_uc to page 1.
Time taken to output .dot file: 431 ms
Total time taken: 45315 ms

End of script. Logfile hash: aed24130cb, CPU: user 45.01s system 0.23s
Yosys 0.34 (git sha1 4a1b5599258, clang 14.0.0 -fPIC -Os)
Time spent: 97% 1x hierarchy (44 sec), 1% 2x read_verilog (0 sec), ...

Answer 1

If you are ready to give it a try, you can test the following tools that I am developping: https://github.com/xtofalex/naja-verilog which is a pure gate level verilog netlist parser (no AST construction) and eventually: https://github.com/xtofalex/naja which is an associated C++ data structure which uses naja-verilog parser for gate-level verilog input and can also be used to construct graphviz like output.

Will be happy to help if you are interested.