What is the cause of Vivados 'synth 8-1027' error?

Question

I imported my ISE 14.7 project into Vivado 2015.1. It had no errors in Xilinx ISE and synthesizes perfectly.

The error is thrown by my entity DMATest from VHDL library L_DMATest.

library IEEE;
use     IEEE.STD_LOGIC_1164.all;
use     IEEE.NUMERIC_STD.all;

library PoC;
use     PoC.my_project.MY_PROJECT_NAME;
use     PoC.config.all;
use     PoC.utils.all;
use     PoC.vectors.all;
use     PoC.strings.all;
use     PoC.physical.all;
use     PoC.io.all;
use     PoC.lcd.all;
use     PoC.sata.all;
use     PoC.satadbg.all;
use     PoC.sata_TransceiverTypes.all;
use     PoC.xil.all;

library L_DMATest;

library L_PicoBlaze;
use     L_PicoBlaze.pb.all;
use     L_PicoBlaze.pb_SoFPGA.all;

entity DMATest is     -- <= line 61
  generic (
    DEBUG                         : BOOLEAN;
    ENABLE_CHIPSCOPE              : BOOLEAN;
    ENABLE_DEBUGPORT              : BOOLEAN;

    SYSTEM_CLOCK_FREQ             : FREQ;
    SATA_CLOCK_FREQ               : FREQ;

    SOFPGA_CLOCK_FREQ             : FREQ;
    UART_CLOCK_FREQ               : FREQ;
    RC_CLOCK_FREQ                 : FREQ;
    IIC_CLOCK_FREQ                : FREQ;

    SATAS_ALLOW_SPEED_NEGOTIATION  : BOOLEAN;
    SATAS_INITIAL_SATA_GENERATION  : T_SATA_GENERATION
  );
  port (
    ClockNetwork_Reset        : in  STD_LOGIC;
    ClockNetwork_ResetDone    : out STD_LOGIC;

    System_Clock              : in  STD_LOGIC;
    System_Reset              : in  STD_LOGIC;
    SoFPGA_Clock              : in  STD_LOGIC;
    SoFPGA_Reset              : in  STD_LOGIC;
    UART_Clock                : in  STD_LOGIC;
    UART_Reset                : in  STD_LOGIC;
    RC_Clock                  : in  STD_LOGIC;
    RC_Reset                  : in  STD_LOGIC;
    IIC_Clock                 : in  STD_LOGIC;
    IIC_Reset                 : in  STD_LOGIC;

    SATA_Clock                : out STD_LOGIC;
    Debug_Clock               : in  STD_LOGIC;
    DebugPortIn               : in  T_SATADBG_STREAMINGSTACK_IN;
    DebugPortOut              : out T_SATADBG_STREAMINGSTACK_OUT;

    UART_TX                   : out STD_LOGIC;
    UART_RX                   : in  STD_LOGIC;

    Raw_IIC_Clock_i           : in  STD_LOGIC;
    Raw_IIC_Clock_t           : out STD_LOGIC;
    Raw_IIC_Data_i            : in  STD_LOGIC;
    Raw_IIC_Data_t            : out STD_LOGIC;
    Raw_IIC_Switch_Reset      : out STD_LOGIC;
    -- vendor specific ports
    SATA_Common_In            : in  T_SATA_TRANSCEIVER_COMMON_IN_SIGNALS;
    SATA_Private_In           : in  T_SATA_TRANSCEIVER_PRIVATE_IN_SIGNALS;
    SATA_Private_Out          : out T_SATA_TRANSCEIVER_PRIVATE_OUT_SIGNALS
  );
end;

architecture rtl of DMATest is          -- <= line 134
  attribute KEEP                      : BOOLEAN;
  attribute ENUM_ENCODING             : STRING;

begin
  -- removed code
end architecture;

The architecture line 134 throws this error:

ERROR: [Synth 8-1027] dmatest is not an entity [D:/git/SATAController/vhdl/ExampleDesign/DMATest/DMATest_DMATest.vhdl:134]

I assume Vivado was not able to parse the entity DMATest, so it's not in the list of known entities.

But how can I narrow down this error?

The error synth 8-1027 has no answer record (AR) on Xilinx.com.

Edit 1:
There is a warning before the 8-1027 error:

WARNING: [Synth 8-2600] re-analyze unit dmatest since unit dmatest is overwritten or removed [D:/git/SATAController/vhdl/ExampleDesign/DMATest/DMATest_DMATest.vhdl:61]

This warning is also unknown to Google :)

I explicitly name all my VHDL libraries (except PoC) L_* to avoid naming collisions. Many VHDL tools don't support libraries named like entities or packages.

Answer 1

Vivado parses all files. Even those which are not used!
My ISE project had a old backup file with a package named 'DMATest' inside it.

This should explain why DMATest was reanalyzed and DMATest is not an entity - it was overridden by the package.