I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I realised that there is no UART available there but it is available from Qsys tool.
My question is about add this IP from a Qsys system.
I don't want to add a NIOS II processor, so I want to controle this IP using the signals (its ports) and not the Avalon MMS function (by registers). I am not sure wether this is possible or not.
Another question, looking for the VHDL template to instatiate the Qsys system I didn't find a .vhd file. How should I instatiate this in my Quartus II design?
To answer your last question, first a) check whether Qsys is generating Verilog or VHDL (if it matters); and b) include your Qsys project files by adding the QIP file to your project found at
<Qsys-project-directory>/synthesis/<qsys-project-name>.qip. The QIP file functions like a header file, listing the names of all the Qsys-generated files for easy inclusion.Qsys also has a tab which details the HDL instantiation for the system.
As for your UART, you have a few options. One possibility is to export the Avalon interface (which makes it available a port to the Qsys module), and then write a simple controller for your IP core to interface with it. Alternatively, you can look into third-party IP (something like http://opencores.org/project,uart2bus maybe?).