modification in UCF file in Xilinx xps

Question

In my ucf file in xps except to the clock of Microblaze I have to add one more clock of my design. I'm not able to understand how to do that. It's giving me warning like:

WARNING:ConstraintSystem:56 - Constraint [system.ucf(13)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named 'clk'.

Here is my ucf file which is giving warning.

NET "CLK_N" LOC = AD11  |  IOSTANDARD = DIFF_SSTL15;

NET "CLK_P" LOC = AD12  |  IOSTANDARD = DIFF_SSTL15;


NET RESET LOC = "AB7"  |  IOSTANDARD = "LVCMOS15";

NET RS232_Uart_1_sin LOC = "M19"  |  IOSTANDARD = "LVCMOS25";

NET RS232_Uart_1_sout LOC = "K24"  |  IOSTANDARD = "LVCMOS25";

NET sm_fan_pwm_net_vcc LOC = "L26"  |  IOSTANDARD = "LVCMOS25";

NET "CLK" TNM_NET = sys_clk_pin;

TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;

CONFIG DCI_CASCADE = "33 32 34";

#######custom ip clk##########

NET "clk" TNM_NET = "clk";

TIMESPEC TS_clk = PERIOD "clk" 5 ns HIGH 50 %;

How to define userip clock in ucf file? I want to give same clock to both Microblaze and my Verilog design.

Answer 1

You have to assign the timing constraint to the clock pin. The clock pin is clk_p (we usually use positive pin for differential) while you try to assign the constraint to clk, which doesn't exist.

Moreover, you have duplicate constraint for the timing net clk. This UCF should work better:

NET "CLK_N" LOC = AD11  |  IOSTANDARD = DIFF_SSTL15;

NET "CLK_P" LOC = AD12  |  IOSTANDARD = DIFF_SSTL15;


NET RESET LOC = "AB7"  |  IOSTANDARD = "LVCMOS15";

NET RS232_Uart_1_sin LOC = "M19"  |  IOSTANDARD = "LVCMOS25";

NET RS232_Uart_1_sout LOC = "K24"  |  IOSTANDARD = "LVCMOS25";

NET sm_fan_pwm_net_vcc LOC = "L26"  |  IOSTANDARD = "LVCMOS25";

NET "CLK_P" TNM_NET = sys_clk_pin;

TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;

CONFIG DCI_CASCADE = "33 32 34";