VHDL: Internal signal in component not triggered

Question

I am new to VHDL. I have this entity (shortened):

entity foo is
  port (CLK   : in  std_logic;
        out_A : out std_logic;
        );
end foo;

architecture Structure of foo is

  component D_Flipflop
    port (
      D     : in  std_logic;
      CLK   : in  std_logic;
      Q     : out std_logic;
      not_Q : out std_logic);
  end component;

  signal D_A, qA, not_qA : std_logic;

begin
  my_Flipflop : D_Flipflop
    port map(
      not_qA,
      CLK,
      qA,
      not_qA
      );
end Structure;

As you can see, I want to use the D_Flipflop like a Toggle-Flipflop, so I redirected the output to the input by the signal not_qA (is that possible?). The problem is that from outside, only the port CLK of foo is visible as input and - at least in the Vivado Simulator - the signals qA and not_qA are never evaluated.

This is the architecture of D_Flipflop:

architecture Behavioral of D_Flipflop is

begin

  set_state : process(CLK, D)
    variable state : std_logic := '0';
  begin
    if falling_edge(CLK) then
      state := D;
      Q     <= state;
      not_Q <= not state;
    end if;
  end process set_state;

end Behavioral;

I googled a lot for this. No chance. Any solutions?

Answer 1

It's not as you indicate in the title to the question that the internal signal to component my_Flipflop didn't trigger, it's that there is no method to provide a known non-meta value state - the not of 'U' is 'U'.

This is caused by the not operator. Refer to the not_table in the body of package std_logic_1164:

    -- truth table for "not" function
    CONSTANT not_table: stdlogic_1d :=
    --  -------------------------------------------------
    --  |   U    X    0    1    Z    W    L    H    -   |
    --  -------------------------------------------------
         ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );

See the changes and the added testbench:

library ieee;                   -- Added Context clause (MCVe)
use ieee.std_logic_1164.all;

entity D_Flipflop is
    port (
        D:      in  std_logic;
        CLK:    in  std_logic;
        Q:      out std_logic; 
        not_Q:  out std_logic := '0'
);
end entity;

architecture behavioral of D_Flipflop is  
begin
set_state:  
    process (CLK)                -- removed D from sensitivity list
        variable state:  std_logic := '0';  
    begin
        if falling_edge(CLK) then
            state := D;
            Q <= state;
            not_Q <= not state;
        end if;
    end process;  
end architecture;

library ieee;                    -- added context clause
use ieee.std_logic_1164.all;

entity foo is
    port (
        CLK:    in  std_logic;
        out_A:  out std_logic     -- removed extra ';'
    );
end entity;

architecture Structure of foo is

    component D_Flipflop is
        port (
            D:      in  std_logic;
            CLK:    in  std_logic;
            Q:      out std_logic;
            not_Q:  out std_logic
      );
  end component;

    -- signal D_A:     std_logic;  -- not used
    signal qA:      std_logic;       
    signal not_qA:  std_logic := '1';  -- notice this didn't matter

begin
my_Flipflop:  
    D_Flipflop
        port map (
            not_qA,
            CLK,
            qA,
            not_qA
        );

    out_A <= qA;                -- Added

end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity foo_tb is
end entity;

architecture fum of foo_tb is
    signal CLK:     std_logic := '0';
    signal out_A:   std_logic;
begin

DUT:
    entity work.foo 
        port map (
            CLK => CLK,
            out_A => out_A
        );
CLOCK:
    process
    begin
        wait for 10 ns;
        CLK <= not CLK;
        if Now > 200 ns then
            wait;
        end if;
    end process;
end architecture;

The not_Q output of the D_Flipflop has been initialized to '0' (it could have as easily been initialized to '1'). This represents the equivalent of a collector set for the Flip Flop on power up.

Now the Flip Flop can toggle - it has a known non-meta value on the D input.

This gives:

(clickable)