What is "top-level HDL wrapper" and why we need to do it in SoC project?
What is "top-level HDL wrapper" means in Vivado SoC?
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You are right, normally in Vivado documentation it is explained how to generate it but not what is it. Well, I guess you use HLD languages (as for example VHDL). You know that you can create different
component
and you canmap
them in your top module HLD entity.Here it is the same: you create a RTL project with your design hardware that needs to be connected to your target board. The WRAPPER is the file that connect the output/input port of your design to the physical pin described in the constraint file.
For example, if you create a simple design with a zynq processor, this one needs to be connected to the DDR, clock, IO_mio pins and so on. In this case, the wrapper should be something like this:
Of course, if you open the file of your board-constraints you will magically discover that the signal-ports are all connected to the physical pins of the FPGA chip.