This line of code gets me confused. I don't get how it works, I know =>
and <=
are assigning symbols, but why 2 assignments to the same thing?
What does it mean whe you have: case state is when vale1 => state <= value2 in vhdl?
250 views Asked by CosnotraLF At
1
As David points out,
=>
is not an assignment symbol.It's a mapping symbol, or an association. Its use is consistent throughout VHDL - it's always used to associate something (often a name) with something else (often a value).
Here, within a case statement, it's used to associate a case choice
when vale1
with the correct action for that state, which can be any valid sequence of statements. In this case,state <= value2;
You may find it clearer to write
which makes the logical structure clearer than trying to do too much in a line.
Other places you'll see it are in parameter lists. Given a function with several parameters (some of which are optional) you may have seen errors creep into programs in other languages where values get associated with the wrong parameters...
You can make it clearer what's going on, and avoid mistakes by associating each parameter with its name :
The same is true of port maps, where you are connecting signals up to the ports of a component.
As David says, another use is in creating aggregates, such as records or arrays.
If you define an Employee record, you might then declare
Or you might create an array using an aggregate: