I have used the XilinX core generator in Vivado 2016.4 to generate the VHDL code for a divider like so:
I have then used the added the template info in div_gen_0.vho like so:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
entity DividingExample is
port (
clk : in std_logic;
reset : in std_logic;
InputSignal : in std_logic_vector(15 downto 0);
OutputSignal : out std_logic_vector(15 downto 0)
);
end DividingExample;
architecture behaviour of DividingExample is
-- declarations
COMPONENT div_gen_0
PORT (
aclk : IN STD_LOGIC;
s_axis_divisor_tvalid : IN STD_LOGIC;
s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_dividend_tvalid : IN STD_LOGIC;
s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
signal numerator : integer;
begin
-- behaviour
DIVIDER : div_gen_0
PORT MAP (
aclk => aclk,
s_axis_divisor_tvalid => s_axis_divisor_tvalid,
s_axis_divisor_tdata => s_axis_divisor_tdata,
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_dividend_tdata => s_axis_dividend_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
process(clk)
begin
if(rising_edge(clk)) then
if(reset = '1') then
-- reset values
numerator <= 1000;
else
-- calculate value to be output
-- OutputSignal <= numerator/to_integer(signed(InputSignal))
end if;
end if;
end process;
end behaviour;
This part compiles fine with GHDL, however the generated synth/div_gen_0.vhd file does not. When compiles with GHDL like so:
ghdl -a synth/div_gen_0.vhd
I get the following output:
synth/div_gen_0.vhd:56:9: cannot find resource library "div_gen_v5_1_11"
synth/div_gen_0.vhd:57:21: unit "div_gen_v5_1_11" not found in 'library "div_gen_v5_1_11"'
And I cannot use the divider as the Divider unit is unbound. Is this an issue I can get around by specifying a different Target Simulator in Vivado or must I use a package like ModelSim in order to use this library?
div_gen_0.vhd contains the following code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY div_gen_v5_1_11;
USE div_gen_v5_1_11.div_gen_v5_1_11;
ENTITY div_gen_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_divisor_tvalid : IN STD_LOGIC;
s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_dividend_tvalid : IN STD_LOGIC;
s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END div_gen_0;
ARCHITECTURE div_gen_0_arch OF div_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF div_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT div_gen_v5_1_11 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ARESETN : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_LATENCY : INTEGER;
ALGORITHM_TYPE : INTEGER;
DIVISOR_WIDTH : INTEGER;
DIVIDEND_WIDTH : INTEGER;
SIGNED_B : INTEGER;
DIVCLK_SEL : INTEGER;
FRACTIONAL_B : INTEGER;
FRACTIONAL_WIDTH : INTEGER;
C_HAS_DIV_BY_ZERO : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_DIVISOR_TUSER : INTEGER;
C_HAS_S_AXIS_DIVISOR_TLAST : INTEGER;
C_S_AXIS_DIVISOR_TDATA_WIDTH : INTEGER;
C_S_AXIS_DIVISOR_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_DIVIDEND_TUSER : INTEGER;
C_HAS_S_AXIS_DIVIDEND_TLAST : INTEGER;
C_S_AXIS_DIVIDEND_TDATA_WIDTH : INTEGER;
C_S_AXIS_DIVIDEND_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_divisor_tvalid : IN STD_LOGIC;
s_axis_divisor_tready : OUT STD_LOGIC;
s_axis_divisor_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_divisor_tlast : IN STD_LOGIC;
s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_dividend_tvalid : IN STD_LOGIC;
s_axis_dividend_tready : OUT STD_LOGIC;
s_axis_dividend_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_dividend_tlast : IN STD_LOGIC;
s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT div_gen_v5_1_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF div_gen_0_arch: ARCHITECTURE IS "div_gen_v5_1_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF div_gen_0_arch : ARCHITECTURE IS "div_gen_0,div_gen_v5_1_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF div_gen_0_arch: ARCHITECTURE IS "div_gen_0,div_gen_v5_1_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=div_gen,x_ipVersion=5.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_XDEVICEFAMILY=kintex7,C_HAS_ARESETN=0,C_HAS_ACLKEN=0,C_LATENCY=36,ALGORITHM_TYPE=1,DIVISOR_WIDTH=32,DIVIDEND_WIDTH=32,SIGNED_B=1,DIVCLK_SEL=1,FRACTIONAL_B=0,FRACTIONAL_WIDTH=32,C_HAS_DIV_BY_ZERO=0,C_THROTTLE_SCHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_DIVISOR_TUSER=0,C_HAS_S_AXIS_DIVISOR_TLAST=0,C_S_AXIS_DIVISOR_TDA" &
"TA_WIDTH=32,C_S_AXIS_DIVISOR_TUSER_WIDTH=1,C_HAS_S_AXIS_DIVIDEND_TUSER=0,C_HAS_S_AXIS_DIVIDEND_TLAST=0,C_S_AXIS_DIVIDEND_TDATA_WIDTH=32,C_S_AXIS_DIVIDEND_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=64,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : div_gen_v5_1_11
GENERIC MAP (
C_XDEVICEFAMILY => "kintex7",
C_HAS_ARESETN => 0,
C_HAS_ACLKEN => 0,
C_LATENCY => 36,
ALGORITHM_TYPE => 1,
DIVISOR_WIDTH => 32,
DIVIDEND_WIDTH => 32,
SIGNED_B => 1,
DIVCLK_SEL => 1,
FRACTIONAL_B => 0,
FRACTIONAL_WIDTH => 32,
C_HAS_DIV_BY_ZERO => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_DIVISOR_TUSER => 0,
C_HAS_S_AXIS_DIVISOR_TLAST => 0,
C_S_AXIS_DIVISOR_TDATA_WIDTH => 32,
C_S_AXIS_DIVISOR_TUSER_WIDTH => 1,
C_HAS_S_AXIS_DIVIDEND_TUSER => 0,
C_HAS_S_AXIS_DIVIDEND_TLAST => 0,
C_S_AXIS_DIVIDEND_TDATA_WIDTH => 32,
C_S_AXIS_DIVIDEND_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 64,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_divisor_tvalid => s_axis_divisor_tvalid,
s_axis_divisor_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_divisor_tlast => '0',
s_axis_divisor_tdata => s_axis_divisor_tdata,
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_dividend_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_dividend_tlast => '0',
s_axis_dividend_tdata => s_axis_dividend_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END div_gen_0_arch;
It is the line LIBRARY div_gen_v5_1_11; that is the problem as Brian points out below. I therefore need the VHDL code to compile to this library the tree structure of the directory created by vivado looks like so:
.
├── cmodel
│ ├── div_gen_v5_1_bitacc_cmodel_lin64.zip
│ └── div_gen_v5_1_bitacc_cmodel_nt64.zip
├── demo_tb
│ └── tb_div_gen_0.vhd
├── div_gen_0.dcp
├── div_gen_0_ooc.xdc
├── div_gen_0_sim_netlist.v
├── div_gen_0_sim_netlist.vhdl
├── div_gen_0_stub.v
├── div_gen_0_stub.vhdl
├── div_gen_0.veo
├── div_gen_0.vho
├── div_gen_0.xci
├── div_gen_0.xml
├── doc
│ └── div_gen_v5_1_changelog.txt
├── hdl
│ ├── axi_utils_v2_0_vh_rfs.vhd
│ ├── div_gen_v5_1_vh_rfs.vhd
│ ├── floating_point_v7_0_vh_rfs.vhd
│ ├── mult_gen_v12_0_vh_rfs.vhd
│ ├── xbip_bram18k_v3_0_vh_rfs.vhd
│ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd
│ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd
│ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd
│ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
│ ├── xbip_pipe_v3_0_vh_rfs.vhd
│ └── xbip_utils_v3_0_vh_rfs.vhd
├── sim
│ └── div_gen_0.vhd
└── synth
└── div_gen_0.vhd
I have discovered, with the help of Brian that the div_gen_0_sim_netlist.vhdl file compiles into the library. This file contains the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity div_gen_0_div_gen_v5_1_11 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_divisor_tvalid : in STD_LOGIC;
s_axis_divisor_tready : out STD_LOGIC;
s_axis_divisor_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_divisor_tlast : in STD_LOGIC;
s_axis_divisor_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_dividend_tvalid : in STD_LOGIC;
s_axis_dividend_tready : out STD_LOGIC;
s_axis_dividend_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_dividend_tlast : in STD_LOGIC;
s_axis_dividend_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tready : in STD_LOGIC;
m_axis_dout_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_dout_tlast : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ALGORITHM_TYPE : integer;
attribute ALGORITHM_TYPE of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_DIV_BY_ZERO : integer;
attribute C_HAS_DIV_BY_ZERO of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TLAST : integer;
attribute C_HAS_S_AXIS_DIVIDEND_TLAST of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TUSER : integer;
attribute C_HAS_S_AXIS_DIVIDEND_TUSER of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_S_AXIS_DIVISOR_TLAST : integer;
attribute C_HAS_S_AXIS_DIVISOR_TLAST of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_HAS_S_AXIS_DIVISOR_TUSER : integer;
attribute C_HAS_S_AXIS_DIVISOR_TUSER of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of div_gen_0_div_gen_v5_1_11 : entity is 36;
attribute C_M_AXIS_DOUT_TDATA_WIDTH : integer;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 64;
attribute C_M_AXIS_DOUT_TUSER_WIDTH : integer;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute C_S_AXIS_DIVIDEND_TDATA_WIDTH : integer;
attribute C_S_AXIS_DIVIDEND_TDATA_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 32;
attribute C_S_AXIS_DIVIDEND_TUSER_WIDTH : integer;
attribute C_S_AXIS_DIVIDEND_TUSER_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute C_S_AXIS_DIVISOR_TDATA_WIDTH : integer;
attribute C_S_AXIS_DIVISOR_TDATA_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 32;
attribute C_S_AXIS_DIVISOR_TUSER_WIDTH : integer;
attribute C_S_AXIS_DIVISOR_TUSER_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of div_gen_0_div_gen_v5_1_11 : entity is 3;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of div_gen_0_div_gen_v5_1_11 : entity is "kintex7";
attribute DIVCLK_SEL : integer;
attribute DIVCLK_SEL of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute DIVIDEND_WIDTH : integer;
attribute DIVIDEND_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 32;
attribute DIVISOR_WIDTH : integer;
attribute DIVISOR_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 32;
attribute FRACTIONAL_B : integer;
attribute FRACTIONAL_B of div_gen_0_div_gen_v5_1_11 : entity is 0;
attribute FRACTIONAL_WIDTH : integer;
attribute FRACTIONAL_WIDTH of div_gen_0_div_gen_v5_1_11 : entity is 32;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of div_gen_0_div_gen_v5_1_11 : entity is "div_gen_v5_1_11";
attribute SIGNED_B : integer;
attribute SIGNED_B of div_gen_0_div_gen_v5_1_11 : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of div_gen_0_div_gen_v5_1_11 : entity is "yes";
end div_gen_0_div_gen_v5_1_11;
architecture STRUCTURE of div_gen_0_div_gen_v5_1_11 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_m_axis_dout_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_dividend_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_divisor_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_dout_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TLAST of i_synth : label is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TUSER of i_synth : label is 0;
attribute C_HAS_S_AXIS_DIVISOR_TLAST of i_synth : label is 0;
attribute C_HAS_S_AXIS_DIVISOR_TUSER of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 36;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of i_synth : label is 64;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of i_synth : label is 1;
attribute C_S_AXIS_DIVIDEND_TDATA_WIDTH of i_synth : label is 32;
attribute C_S_AXIS_DIVIDEND_TUSER_WIDTH of i_synth : label is 1;
attribute C_S_AXIS_DIVISOR_TDATA_WIDTH of i_synth : label is 32;
attribute C_S_AXIS_DIVISOR_TUSER_WIDTH of i_synth : label is 1;
attribute C_THROTTLE_SCHEME of i_synth : label is 3;
attribute C_TLAST_RESOLUTION of i_synth : label is 0;
attribute algorithm_type of i_synth : label is 1;
attribute c_has_div_by_zero of i_synth : label is 0;
attribute c_xdevicefamily of i_synth : label is "kintex7";
attribute divclk_sel of i_synth : label is 1;
attribute dividend_width of i_synth : label is 32;
attribute divisor_width of i_synth : label is 32;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
attribute fractional_b of i_synth : label is 0;
attribute fractional_width of i_synth : label is 32;
attribute signed_b of i_synth : label is 1;
begin
m_axis_dout_tlast <= \<const0>\;
m_axis_dout_tuser(0) <= \<const0>\;
s_axis_dividend_tready <= \<const1>\;
s_axis_divisor_tready <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.div_gen_0_div_gen_v5_1_11
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
m_axis_dout_tdata(63 downto 0) => m_axis_dout_tdata(63 downto 0),
m_axis_dout_tlast => NLW_i_synth_m_axis_dout_tlast_UNCONNECTED,
m_axis_dout_tready => '0',
m_axis_dout_tuser(0) => NLW_i_synth_m_axis_dout_tuser_UNCONNECTED(0),
m_axis_dout_tvalid => m_axis_dout_tvalid,
s_axis_dividend_tdata(31 downto 0) => s_axis_dividend_tdata(31 downto 0),
s_axis_dividend_tlast => '0',
s_axis_dividend_tready => NLW_i_synth_s_axis_dividend_tready_UNCONNECTED,
s_axis_dividend_tuser(0) => '0',
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_divisor_tdata(31 downto 0) => s_axis_divisor_tdata(31 downto 0),
s_axis_divisor_tlast => '0',
s_axis_divisor_tready => NLW_i_synth_s_axis_divisor_tready_UNCONNECTED,
s_axis_divisor_tuser(0) => '0',
s_axis_divisor_tvalid => s_axis_divisor_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity div_gen_0 is
port (
aclk : in STD_LOGIC;
s_axis_divisor_tvalid : in STD_LOGIC;
s_axis_divisor_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_dividend_tvalid : in STD_LOGIC;
s_axis_dividend_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of div_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of div_gen_0 : entity is "div_gen_0,div_gen_v5_1_11,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of div_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of div_gen_0 : entity is "div_gen_v5_1_11,Vivado 2016.4";
end div_gen_0;
architecture STRUCTURE of div_gen_0 is
signal NLW_U0_m_axis_dout_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_dividend_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_divisor_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_dout_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TLAST : integer;
attribute C_HAS_S_AXIS_DIVIDEND_TLAST of U0 : label is 0;
attribute C_HAS_S_AXIS_DIVIDEND_TUSER : integer;
attribute C_HAS_S_AXIS_DIVIDEND_TUSER of U0 : label is 0;
attribute C_HAS_S_AXIS_DIVISOR_TLAST : integer;
attribute C_HAS_S_AXIS_DIVISOR_TLAST of U0 : label is 0;
attribute C_HAS_S_AXIS_DIVISOR_TUSER : integer;
attribute C_HAS_S_AXIS_DIVISOR_TUSER of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 36;
attribute C_M_AXIS_DOUT_TDATA_WIDTH : integer;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of U0 : label is 64;
attribute C_M_AXIS_DOUT_TUSER_WIDTH : integer;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of U0 : label is 1;
attribute C_S_AXIS_DIVIDEND_TDATA_WIDTH : integer;
attribute C_S_AXIS_DIVIDEND_TDATA_WIDTH of U0 : label is 32;
attribute C_S_AXIS_DIVIDEND_TUSER_WIDTH : integer;
attribute C_S_AXIS_DIVIDEND_TUSER_WIDTH of U0 : label is 1;
attribute C_S_AXIS_DIVISOR_TDATA_WIDTH : integer;
attribute C_S_AXIS_DIVISOR_TDATA_WIDTH of U0 : label is 32;
attribute C_S_AXIS_DIVISOR_TUSER_WIDTH : integer;
attribute C_S_AXIS_DIVISOR_TUSER_WIDTH of U0 : label is 1;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of U0 : label is 3;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of U0 : label is 0;
attribute algorithm_type : integer;
attribute algorithm_type of U0 : label is 1;
attribute c_has_div_by_zero : integer;
attribute c_has_div_by_zero of U0 : label is 0;
attribute c_xdevicefamily : string;
attribute c_xdevicefamily of U0 : label is "kintex7";
attribute divclk_sel : integer;
attribute divclk_sel of U0 : label is 1;
attribute dividend_width : integer;
attribute dividend_width of U0 : label is 32;
attribute divisor_width : integer;
attribute divisor_width of U0 : label is 32;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute fractional_b : integer;
attribute fractional_b of U0 : label is 0;
attribute fractional_width : integer;
attribute fractional_width of U0 : label is 32;
attribute signed_b : integer;
attribute signed_b of U0 : label is 1;
begin
U0: entity work.div_gen_0_div_gen_v5_1_11
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
m_axis_dout_tdata(63 downto 0) => m_axis_dout_tdata(63 downto 0),
m_axis_dout_tlast => NLW_U0_m_axis_dout_tlast_UNCONNECTED,
m_axis_dout_tready => '0',
m_axis_dout_tuser(0) => NLW_U0_m_axis_dout_tuser_UNCONNECTED(0),
m_axis_dout_tvalid => m_axis_dout_tvalid,
s_axis_dividend_tdata(31 downto 0) => s_axis_dividend_tdata(31 downto 0),
s_axis_dividend_tlast => '0',
s_axis_dividend_tready => NLW_U0_s_axis_dividend_tready_UNCONNECTED,
s_axis_dividend_tuser(0) => '0',
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_divisor_tdata(31 downto 0) => s_axis_divisor_tdata(31 downto 0),
s_axis_divisor_tlast => '0',
s_axis_divisor_tready => NLW_U0_s_axis_divisor_tready_UNCONNECTED,
s_axis_divisor_tuser(0) => '0',
s_axis_divisor_tvalid => s_axis_divisor_tvalid
);
end STRUCTURE;