I'm trying to find out how could I check if a 3-bit bus has the msb set on 1, i.e. 1xx. When I check bus==3'b1xx nothing seems to happen.
How to test if a 3-bit bus has the first bit set on 1 - verilog
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The result of the expression you wrote can only be (1'b0) or (1'bx), which are both considered false for an
ifstatement branch.Assuming you declared the bus as
wire [2:0] bus;you can check it usingbus[2] == 1'b1Now in SystemVerilog, you can do a wildcard match using
bus ==? 3'b1xxwhich treats the RHS X's as don't cares. X's on the LHS are treated the same as==.