Why isn't ModelSIM displaying timing waveforms, whereas GTKWave does?

Question

I am kinda new to verilog and struggling with all the basic concepts. I am trying to display the timing waveform in ModelSim, where is simply throws "# (vish-4014) No objects found matching '/tb/*'. "(in my case).

Whereas when I simulate the testbench in VSCode, using icarus & gkwave, it displays the necessary waveforms I require. In VS Code, I run

iverilog -o tb.vvp tb.v 
vvp tb.vvp
gtkave

GTKwave pops up and shows the waveforms. The hardware I am testing out takes 2 numbers as inputs and returns the small and large number (cnsmodule attached below). The testbench I am simulating is named "tb.v" and goes as:

module tb();
reg a0,a1,a2,a3;
wire s0,s1,s2,s3;

level uu(.*);
always begin
    $dumpfile("tb.vcd");
    $dumpvars(0,tb);
  
    a0=2'b01;a1=2'b00;a2=2'b11;a3=2'b10;
    #10;
    
    $finish;
  
end 
endmodule

The relevant modules I am instantiating are:

// Instantiates 3 cnsmodules to input 4 numbers and return them from small to large    
module level(a0,a1,a2,a3,s0,s1,s2,s3);

input a0,a1,a2,a3;
output s0,s1,s2,s3;

wire s0,s1,s2,s3;
wire temp1,temp2;

cnsmodule tvz1(a0,a1,s0,temp1);
cnsmodule tvz2(temp1,a2,s1,temp2);
cnsmodule tvz3(temp2,a3,s2,s3);

endmodule

and:

    module cnsmodule (a0,a1,sn,ln);
  input a0,a1;
  output sn,ln;
  reg sn,ln;

  always@(*) begin
    if (a0>a1) begin 
      sn=a1; ln=a0;
    end
    
  else begin 
    sn=a0; ln=a1;
  end
end
endmodule

Answer 1

I suspect that your problem lies with the optimization ModelSIM does to the design, Try the following and tell me if that works in the top bar click on simulate and then followed by optimization options and then click on "Apply full visibillity to all modules(full debug mode)" and then choose your testbench and try to add your signals now