VHDL , Spartan-3AN output

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I have this design which basically about a multifunctional calender that have the following features:

  1. displays the date in this [ format year/month/day : hours : minutes : seconds ]
  2. Stop watch.
  3. Alarm .
  4. A Snooz option when the alarm is active , and you can change the snooz period or you can stop the alarm .
  5. events , to be saved in a selected date and time and when it occur an alarm will be enabled.

this is what i have done for calculating the clock [ hours : minutes : seconds ]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clock is
port (clk : in std_logic;
      seconds : out integer ;
      minutes : out integer;
      hours : out integer
     );
end Clock;

architecture Behavioral of Clock is
        signal sec,min : integer range 0 to 60 := 0 ;
        signal hour : integer range 0 to 24 := 0 ;
begin
        seconds <= sec;
        minutes <= min;
        hours <= hour;

        process (clk)
        begin
            if (clk'event and clk='1') then
                sec <=sec+1 ;
                if (sec=60) then 
                    min <= min+1 ;
                    sec <= 0 ;
                    if (min=60) then 
                        hour <= hour +1;
                        min<=0;
                        if ( hour = 24) then
                            hour <= 0;
                        end if;
                    end if ;
                end if;
            end if;
        end process ;

end Behavioral;

and this code to do the rest date information [Year/month/day] ...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity calender is
   port (
        clk : in std_logic;
      LYear     : in  std_logic;
      O_DAYS_IN_MONTH : out unsigned(4 downto 0)
      );
end entity calender;

architecture Behavioral of calender is

    signal hours :integer;
    signal Mday,day : integer range 1 to 31:=1;
    signal month: integer range 1 to 12:=1;
    signal year : integer range 2010 to 2030 :=2010;

begin
    u0 : entity work.Clock port map ( clk => clk , hours => hours );

    process ( clk,hours )
    begin 
        if (clk'event and clk='1') then
            if ( hours = 23 ) then 
                day <= day +1 ;
                if ( day = Mday ) then 
                    day <= 1;
                    month <= month +1 ;
                    if ( month = 13 ) then 
                        month <= 1 ;
                        year <= year +1;
                        if ( year = 2030 ) then 
                            year <= 2010;
                        end if;
                    end if;
                end if;
            end if;
        end if;
    end process;

    process ( month , LYear)
    begin
        if ( month = 9  or month = 4 or month = 6 or  month = 11) then 
            Mday <= 30;
        elsif ( month = 2 and LYear = '0') then 
            Mday <= 28 ;
        elsif ( month = 2 and LYear = '1') then 
            Mday <= 29;
        else 
            Mday <= 31;
        end if;
    end process;

   O_DAYS_IN_MONTH <= to_unsigned( Mday ,O_DAYS_IN_MONTH'length) ;                   

end architecture Behavioral;

I'v also the coded for the stop watch independently , that out puts on the 7-Segment in the spartan 3 which is the following ...

library IEEE;                                                       
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity stop_watch is
port(
        clr: in std_logic;
        strt: in std_logic;
        clk : in std_logic;
        anode : out std_logic_vector (3 downto 0);
        seg : out std_logic_vector (7 downto 0)
        ); 
end stop_watch ;

architecture Behavioral of stop_watch is
    signal dig1,dig2,dig3,dig4:std_logic_vector (7 downto 0);
    signal clk10hz,clk1khz:std_logic;
begin


    process (clr,strt,clk10hz)
        variable d1,d2,d4:integer range 0 to 10;
        variable d3:integer range 0 to 6;
     begin
        if(clr='1')then
            d1:=0;
            d2:=0;
            d3:=0;
            d4:=0;
        elsif(clk10hz'event and clk10hz='1') then
            if(strt='0')then
                d1:=d1;
                d2:=d2;
                d3:=d3;
                d4:=d4;
            else
                d1:= d1+1;
                if(d1=10)then
                    d1:=0;
                    d2:=d2+1;
                end if;
                if(d2=10)then
                    d3:=d3+1;
                    d2:=0;
                end if;
                if(d3=6)then
                    d4:=d4+1;
                    d3:=0;
                end if; 
                if(d4=10)then
                    d4:=0;
                end if;
            end if;
        end if; 


        case d1 is 
            when 0 => dig1 <="10000001";
            when 1 => dig1 <="11001111";
            when 2 => dig1 <="10010010";
            when 3 => dig1 <="10000110";
            when 4 => dig1 <="11001100";
            when 5 => dig1 <="10100100";
            when 6 => dig1 <="10100000";
            when 7 => dig1 <="10001111";
            when 8 => dig1 <="10000000";
            when 9 => dig1 <="10001100";
            when 10 => dig1 <="10000001";
        end case;

        case d2 is
            when 0 => dig2 <="00000001";
            when 1 => dig2 <="01001111";
            when 2 => dig2 <="00010010";
            when 3 => dig2 <="00000110";
            when 4 => dig2 <="01001100";
            when 5 => dig2 <="00100100";
            when 6 => dig2 <="00100000";
            when 7 => dig2 <="00001111";
            when 8 => dig2 <="00000000";
            when 9 => dig2 <="00001100";
            when 10 => dig2 <="00000001";
        end case;

        case d3 is 
            when 0 => dig3 <="10000001";
            when 1 => dig3 <="11001111";
            when 2 => dig3 <="10010010";
            when 3 => dig3 <="10000110";
            when 4 => dig3 <="11001100";
            when 5 => dig3 <="10100100";
            when 6 => dig3 <="10100000";
        end case;

        case d4 is
            when 0 => dig4 <="00000001";
            when 1 => dig4 <="01001111";
            when 2 => dig4 <="00010010";
            when 3 => dig4 <="00000110";
            when 4 => dig4 <="01001100";
            when 5 => dig4 <="00100100";
            when 6 => dig4 <="00100000";
            when 7 => dig4 <="00001111";
            when 8 => dig4 <="00000000";
            when 9 => dig4 <="00001100";
            when 10 => dig4 <="00000001";
        end case;
    end process;


    process (clk)
        Variable Count: integer range 0 to 5000000 :=0;
    begin
        if (Clk'event and Clk ='1') then
            count := count+1;
            if ( count < 2500000 ) then
                clk10Hz <= '0';
            elsif (count = 2500000) then
                clk10Hz <= '1';
            elsif (count = 5000000) then
                clk10Hz <= '0' ; count := 0;
            end if; 
        end if;
    end process ;


    process (clk1Khz)
        variable cnt : integer range 0 to 3:= 0;
    begin
        if (clk1Khz'event and clk1Khz='1') then
            case cnt is
                when 0 => anode <="1110";
                    seg<= dig1;
                    cnt:=cnt+1;
                when 1 => anode <="1101";
                    seg<= dig2;
                    cnt:=cnt+1;
                when 2 => anode <="1011";
                    seg<= dig3;
                    cnt:=cnt+1;
                when 3 => anode <="0111";
                    seg <= dig4;
                    cnt:=0;
                end case;
        end if;
   end process;


    process (clk)
        Variable Count: integer range 0 to 50000 :=0;
    begin
        if (Clk'event and Clk ='1') then
            count := count+1;
            if ( count < 25000 ) then
                clk1Khz <= '0';
            elsif (count = 25000) then
                clk1Khz <= '1';
            elsif (count = 50000) then
                clk1Khz <= '0' ; count := 0;
            end if; 
        end if;
    end process ;


end     Behavioral; 

Now , My problem is ..

I'm supposed to out put all this information's on the LCD display in the spartan 3-AN , which i totally have no experience with , i know that my code still not finished yet and still have to do some clock divisions as i did in the stop watch code , and i know that the clock divisions will be changed when interaction with the LCD so i didn't bother writing it in my code write now. If anyone can give me any informations about how to deal with the LCD display , how to display characters , how move from character to another so i can change it when an event happens from a keyboard.

You can say that i have 0 experience with dealing with that LCD in Spartan 3AN , i have tried to see the user guide for the board that xilinx provided and i have understood some few things from it but still don't know how to use it , if there is any tutorial that can help will be more than enough for me.

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