Error with wait conditions

Question

I am a beginner to VHDL, and I am trying to make a multiplier, but the code I have to use from the book is not compiling right with the xilinx software. The code is:

     library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testMult is
    Port ( ISwitch  : in  STD_LOGIC_VECTOR (3 downto 0);
           IPress : in  STD_LOGIC;
           IRegIn : in  STD_LOGIC_VECTOR (31 downto 0);
           IRegOut : out  STD_LOGIC_VECTOR (31 downto 0);
           Iclk : in  STD_LOGIC);
end testMult;

architecture Beh of testMult is
    component asMult
        port(ISwitch  : in  STD_LOGIC_VECTOR (3 downto 0);
           IRegA : in  STD_LOGIC_VECTOR (7 downto 0);
              IRegB : in STD_LOGIC_VECTOR (7 downto 0);
           IRegProd : out  STD_LOGIC_VECTOR (15 downto 0);
           Iclk : in  STD_LOGIC;
              St : in STD_LOGIC;
              Done : out STD_LOGIC);
    end component;

constant aValue : std_logic_vector:= IRegIn(7 downto 0);
constant bValue : std_logic_vector:= IRegIn(15 downto 8);
signal Done : std_logic;
signal St : std_logic;
signal IRegA, IRegB : std_logic_vector(7 downto 0);
signal IRegProd : std_logic_vector(15 downto 0);
signal CLK : std_logic;

begin

CLK <= not CLK after 10 ns;

process
    begin
        if IPress = '1' then
            IRegA <= aValue;
            IRegB <= bValue;
            St <= '0';
        wait until CLK = '1' and CLK'event;
            St <= '1';
        wait until Done = '0' and Done'event;
            IRegOut <= IRegProd & IRegIn(15 downto 8) & IRegin(7 downto 0);
        end if;
end process;
asMult1 : asMult port map (ISwitch, aValue, bValue, IRegProd, Iclk, St, Done);
end Beh;

But I keep getting this error: line 36: Same wait conditions expected in all Multiple Waits.

Answer 1

Are you trying to synthesize that code, or you just want to simulate it? The code won't synthesize because:

1. CLK <= not CLK after 10 ns is not a synthesizable statement, and
2. The synthesis tools are equiped to handle only simpler kinds of processes. Try to break up your code into processes that are either purely combinational, or synchronous processes sensitive to the same edge of the same clock.

If you only want to simulate the code, there are still other problems with your example, but at least it compiles ok with Modelsim ASE 10.1b. My guess would be your compiler is trying to synthesize the code.

Answer 2

That's simulation code - you can run a simulation in ISIM.

After you have that working, you can synthesise part of it (the asmult block), but you can't synthesise your top level block as it is full of test-bench, simulation-only, code, like waiting on events (which can only be done in very specific ways for synthesis) and after.