Counters VHDL multiplexer 7 segment

Question

I am new to VHDL and my code may seem stupid but I am still struggling. I am trying to make a BCD counter using Spartan 3 kit. I have a problem multiplexing the 7 segment, and I know i should use components but I went with the easier way. I get this error in synthesis: "line 103: One or more signals are missing in the process sensitivity list". To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: any help appreciated. Thank you.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab5 is
  port (clk      : in  std_logic;
        x        : in  std_logic;
        --count : inout  STD_LOGIC_VECTOR (3 downto 0);
        data_out : out std_logic_vector (6 downto 0);
        an       : out std_logic_vector (3 downto 0)
        );

end lab5;

architecture Behavioral of lab5 is
  signal counter    : std_logic_vector (3 downto 0) := (others => '0');
  signal prescaler  : std_logic_vector (25 downto 0);
  signal prescaler2 : std_logic_vector (11 downto 0);
  signal counter2   : std_logic_vector (1 downto 0) := (others => '0');
begin

  CounterProcess : process(CLK, x)
  begin
    --prescaler is used as a clock slower to increment the counter every 50M cycles(1 sec)
    if rising_edge(CLK) then
      if prescaler < "10111110101111000010000000" then
        prescaler <= prescaler+1;

      else
        prescaler <= (others => '0');
        if x = '0' then
          if counter = "1001" then
            counter <= "0000";
          else
            counter <= counter+1;
          end if;
        else
          if counter = "0000" then
            counter <= "1001";
          else
            counter <= counter-1;
          end if;
        end if;
      end if;
    end if;

  end process;

--count<=counter;

  Sevensegclock : process(CLK)
  begin
    if rising_edge(CLK) then
      --scale clock to count(which will be the segment selector) every 1024 cycle
      if prescaler2 < "010000000000" then
        prescaler2 <= prescaler2+1;

      else
        prescaler2 <= (others => '0');
        if counter2 = "11" then
          counter2 <= "00";
        else
          counter2 <= counter2+1;
        end if;
      end if;
    end if;

  end process;

  sevenseg : process(counter2, clk)
  begin
    --counter the segment selector used to activate selector and decode data
    if counter2 = "00" then
      an <= "1110";
      if counter(0) = '0' then
        data_out <= "0000001";
      else
        data_out <= "1001111";
      end if;

    end if;

    if counter2 = "01" then
      an <= "1101";
      if counter(1) = '0' then
        data_out <= "0000001";
      else
        data_out <= "1001111";
      end if;
    end if;

    if counter2 = "10" then
      an <= "1011";

      if counter(2) = '0' then
        data_out <= "0000001";
      else
        data_out <= "1001111";
      end if;
    end if;

    if counter2 = "11" then
      an <= "0111";
      if counter(3) = '0' then
        data_out <= "0000001";
      else
        data_out <= "1001111";
      end if;
    end if;

  end process;

end Behavioral;

Answer 1

One place to start, is for each of the processes to determine if it implements a sequential element (flip-flop) or a combinatorial element (gates).

The template for a process that implements a sequential element (flip-flop), without asynchronous reset, can be:

process (clk) is
begin
  if rising_edge(clk) then
    -- Code for assign to flip-flop outputs at rising edge
  end if;
end process;

The template for a process that implements a combinatorial element (gates), can be:

process (all) is  -- "all" make sensitivity on all used signals
begin
  -- Code for assign to gate outputs
end process;

Note that (all) is usable in VHDL-2008 syntax only, else for previous VHDL version syntax list all signals explicitly in sensitivity list

Matching one of the templates makes the synthesis tool determine how to implement the design described in the VHDL code. However, if the code matches neither of the templates, then the synthesis tool may have difficulties determine how to implement the VHDL code in the FPGA, and the result may be a error message, as the one you get.

Based on the templates, the process Sevensegclock implements a sequential element (flip-flop), and there should be no issues with this process.

However, the processes CounterProcess and sevenseg does not match either of the templates for sequential or combinatorial element.

For the process CounterProcess, it looks like you want to implement a sequential element (flip-flop), but the sensitivity list has x included. The solution is then probably to remove the x from the sensitivity list.

For the process sevenseg, it looks like you want to implement a combinatorial element (gates), but the sensitivity list does not cover all the signals used in the process, and even includes the clk which is not used in the process. The solution if you are using VHDL-2008 is to replace the sensitivity list with (all), and if using previous VHDL versions the make the sensitivity list cover all the signals used in the process (counter2, counter).

Disclaimer: I have not checked the logical correctness of the code in the process; so the above is only to give some general guidelines for how to write processes in order to make different kind of design elements in the FPGA.