In synopsys VCS, how can I get the raw RTL verilog output file?

Question

I need the VCS preprocessor output. Theres a way to get a verilog file where all params and macros are filled in from the preprocessor. How do I do that?

Answer 1

I found an answer online. vppreproc command will flatten all macros/defines.

https://metacpan.org/pod/distribution/Verilog-Perl/vppreproc

Answer 2

In vcs you can use the -Xman=28 qualifier. It will generate a token file with expanded macros.

From the manual:

Produces a mangled version of input, changing variable names to words from list. Useful to get an entire Verilog design into a single file. Output is saved in the tokens.v file. You can substitute -Xman for -Xmangle. The argument number can be 1, 4, 12, or 28: -Xman=1 Randomly changes names and identifiers, and removes comments, to provide more secure code. -Xman=4 Preserves variable names, but removes comments. -Xman=12 Does the same thing as -Xman=4, but also enters, in comments, the original source file name and the line number of each module header. -Xman=28 Does the same thing as -Xman=12, but also writes at the bottom of the file comprehensive statistics about the contents of the original source file.