Creation of array in Verilog that can store real values

Question

Could anyone tell me how to create an array that can store real values in Verilog? I tried the following, but it did not work:

real [31:0] in1_table [0:256];

Answer 1

One way is to use an unpacked array. Change:

real [31:0] in1_table [0:256];

to:

real in1_table [31:0] [0:256];

This works for me with 2 different simulators:

module tb;

real in1_table [31:0] [0:256];

initial begin
    in1_table[0][0] = 5.666;
    in1_table[0][1] = 16.67;
    $display(in1_table[0][0]);
    $display(in1_table[0][1]);
end

endmodule

Output:

5.666
16.67

Refer to IEEE Std 1800-2012, section 7.4 "Packed and unpacked arrays".

From "7.4.1 Packed arrays"

Packed arrays can be made of only the single bit data types (bit, logic, reg), enumerated types, and recursively other packed arrays and packed structures.

I interpret this to mean that packed arrays of type real are not permitted.

This assumes you wanted a multi-dimensional array of reals (32x257 reals).

Answer 2

If you want a 32-bit real, you need to use shortreal, otherwise real is 64-bits. Those are your only two options for real numbers. The range [31:0] you wrote is considered a packed array range, which is only valid for integral types.