importing VHDL packages to SV from libraries other than WORK

Question

I have a VHDL module that is compiled to a library, say, LIB_A. The module has ports that are records, the corresponding type is defined in a package that is also compiled into LIB_A. I would like to write some assertions for the module and check them using OneSpin.

At the moment I have the problem that I can access the simple ports of the module in SV, but I cannot access the ports that are record elements. I tried to import the VHDL package with import and different combinations of library/package names, but it didn't work.

What is exactly the syntax of importing a VHDL package from the library LIB_A? Do I have to consider anything else?

The code example:

import my_package::*; // LIB_A?

module checker_m;


// 
// A plain SVA assertion
// 
always dummy_a: assert ( my_module.record_output.Reg1.some_sig == 0 );


endmodule

bind my_module checker_m checker_inst ();

Answer 1

The problem seems to be indeed vendor-specific, as @toolic mentioned. For some reasons it works when I write the record elements in the lower case. The rest (signals, modules) I wrote in the same case as it was in VHDL, and it worked. Only the record elements caused problems until they were written in the lower case.