Verilog generate statement : conditional port connections

Question

I'm declaring several modules with the ports connected as follows:

mymodule m0 ( .a(myreg[0]), .b(myreg[3]), .c(2'd0), .d(oreg1));
mymodule m1 ( .a(myreg[1]), .b(myreg[0]), .c(2'd1), .d(oreg1));
mymodule m2 ( .a(myreg[2]), .b(myreg[1]), .c(2'd2), .d(oreg1));
mymodule m3 ( .a(myreg[3]), .b(myreg[2]), .c(2'd3), .d(oreg2));

I am trying to use a generate statement but can't figure out how to get the connections rights.

genvar i;
generate
for(i=0; i<3; i=i+1) begin : mymodules
    mymodule m (.a(myreg[i]), .b(???), .c(???), .d(???);
end
endgenerate

In my example above port a is easy enough, but the others I'm not sure how to handle. Any suggestions for how to take care of b, c, and d? Thanks!

Answer 1

For the port connections from a sequence of 0,1,2,3 you need to generate the following sequence 3,0,1,2. The transfer function is +3 modulus 4.

genvar i;
generate
for(i=0; i<=3; i=i+1) begin : mymodules
    mymodule m (.a(myreg[i]), .b(myreg[(i+3)%4]), .c(i[1:0]), .d(???));
end
endgenerate

Also note that you want your loop to run for <4 or <=3 at present it is only running from 0 until 2 (<3). And your missing a final ) from the instantiation.

For the oregX d input not sure if there is a pattern being followed or a simple if statement would work.

genvar i;
generate
for(i=0; i<=3; i=i+1) begin : mymodules
   if (i<3) begin
    mymodule m (.a(myreg[i]), .b(myreg[(i+3)%4]), .c(i[1:0]), .d(oreg1));
   end
   else begin
     mymodule m (.a(myreg[i]), .b(myreg[(i+3)%4]), .c(i[1:0]), .d(oreg2));
   end
end
endgenerate

toolic suggested first creating a wire then hooking that up bit by bit:

wire [3:0] d = {oreg2,{3{oreg1}}};
genvar i;
generate
for(i=0; i<=3; i=i+1) begin : mymodules
    mymodule m (.a(myreg[i]), .b(myreg[(i+3)%4]), .c(i[1:0]), .d(d[i]);
end
endgenerate