How to find the maximum frequency a RTL code support?

Question

I have a very basic question, How do we conclude the maximum freqency my synthesizable RTL code support? where do we check it in Vivado , quartus and Yosys tools

Answer 1

In case of Yosys it is better to use another open source tool like opensta which has its repository in the following link https://github.com/The-OpenROAD-Project/OpenSTA, an example for a simple script you can run on that tool to get your timing checks is as follows

read_liberty <standard_cell_library_name>
read_verilog <name_of_verilog_file(s))
link_design <name_of_top_module>
create_clock -name clk -period 10 {<name_of_clock_inside_your_module>}
report_checks

You can also check their documentation to see how you can do more advanced scripts if you want