How do I diagnose and fix COMP96 ERROR COMP96_0055 and COMP96 ERROR COMP96_0056 when using Vunit to run my VHDL test bench

Question

EDIT: After double checking my files, the issue was within the run.py. My other run.py files had this,

VU = VUnit.from_argv()
VU.enable_location_preprocessing()

whereas the one I was using for this project had the following,

VU = VUnit.from_argv(compile_builtins=False)
VU.enable_location_preprocessing()

This was done as a response to the following notification.

WARNING - Option 'compile_builtins' of methods 'from_args' and 'from_argv' is deprecated.
In future releases, it will be removed and builtins will need to be added explicitly.
To prepare for upcoming changes, it is recommended to apply the following modifications in the run script now:

* Use `from_argv(compile_builtins=False)` or `from_args(compile_builtins=False)`.
* Add an explicit call to 'add_vhdl_builtins'.

Clearly, I did not implement this change correctly. It should be,

VU = VUnit.from_argv(compile_builtins=False)
# Add VUnit VHDL built-in libraries
VU.add_vhdl_builtins()
VU.enable_location_preprocessing()

_________________________________________________________________________________________________________

I am brushing up on my VHDL skills and I am putting together a test bench for an SPI controller module. I am using vunit to run the testbench with the ActiveHDL simulator. When compiling, I get the following errors from vunit.

=== Command output: ===
COMP96 ERROR COMP96_0055: "Cannot find context item "vunit_lib.vunit_context"." "C:\Projects\VHDL_Projects\SPI_CTRL\vunit_out\preprocessed\design_lib\SPI_CTRL_tb.vhd" 18 19
COMP96 ERROR COMP96_0056: "Cannot find referenced entity declaration "SPI_CTRL_tb"." "C:\Projects\VHDL_Projects\SPI_CTRL\vunit_out\preprocessed\design_lib\SPI_CTRL_tb.vhd" 32 1
COMP96 Compile failure 2 Errors 0 Warnings  Analysis time :  15.0 [ms]

Here is the code. Please note that this is not a completed test bench, as its not testing anything but it should still compile.

library vunit_lib;
context vunit_lib.vunit_context;
library IEEE;
use IEEE.STD_LOGIC_1164.all;


entity SPI_CTRL_tb is
  generic (
    CLK_PERIOD  : time := 10 ns;
   -- HALF_PERIOD : time := (CLK_PERIOD / 2);
    runner_cfg  : string;
    N           : integer := 8
);
end entity;

architecture BEHAVE of SPI_CTRL_tb is

  -- Stimulus signals - signals mapped to the input and inout ports of tested entity
  signal CLK               : std_logic := '0';
  signal RSTB              : std_logic := '0';
  signal TX_START          : std_logic := '0';
  signal MISO              : std_logic := '0';
  signal DATA_PARALLEL_SND : std_logic_vector(N-1 downto 0) := "00000000";
    
  -- Observed signals - signals mapped to the output ports of tested entity
  signal TX_END            : std_logic; 
  signal DATA_PARALLEL_RSV : std_logic_vector(N-1 downto 0);
  signal SCLK              : std_logic;
  signal CS                : std_logic;
  signal MOSI              : std_logic;

begin

  -- Clock and reset generation N/A
  CLK  <= not CLK after CLK_PERIOD / 2;
  RSTB <= '1' after 2 * CLK_PERIOD;

  -- Unit Under Test instantiation
  UUT : entity work.SPI_CTRL
  generic map(
    N => N,          -- Set N to the desired value
    CLK_DIV => 100   -- Set CLK_DIV to the desired value
  )
  port map (
    CLK_IN           => CLK,
    RSTB_IN          => RSTB,
    TX_START_IN      => TX_START,
    MISO_IN          => MISO,
    DATA_PARALLEL_IN => DATA_PARALLEL_SND,
  
    TX_END_OUT        =>TX_END,
    DATA_PARALLEL_OUT =>DATA_PARALLEL_RSV,
    SCLK_OUT          =>SCLK,
    CS_OUT            =>CS,
    MOSI_OUT          =>MOSI
    );

  -----------------------------------------------------------------------
  -- TEST_STIMULUS : generates the test inputs to the simulation
  -----------------------------------------------------------------------
  TEST_STIMULUS : process
  begin
      test_runner_setup(runner, runner_cfg);
      disable_stop(error);
 
 
    -- Remove these two lines of code when you are ready to implement your own tests
    -- wait for 1 us;
    -- std.env.stop;
    check_equal(true,false,"Blagh");

    
    test_runner_cleanup(runner);

  end process TEST_STIMULUS;


end BEHAVE;

If I comment out context vunit_lib.vunit_context; then COMP96 ERROR COMP96_0056 will go away and, once I have removed all vunit specific code, it will compile. I have other projects with test benches structured similarly but none of them have this issue with the context vunit_lib.vunit_context; line.