can cadence netlister si produce a flat verilog netlist?

Question

i have a cadence schematic with hierarchy. i am able to run the si netlister in batch mode at the command line to produce a hierarchical verilog netlist. i was wondering if anyone knows if it is possible to produce a flat verilog netlist. i have tried various options but can't seem to get it to work. searches on google seem to give mixed opinions of whether this is possible or not.

my si.env file for the hierarchical run is below:

simLibName = "myLib"
simCellName = "myCell"
simViewName = "schematic"
simSimulator = "verilog"
simNotIncremental = 't
simReNetlistAll = 't
simViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simStopList = '("functional" "verilog" "symbol")
simNetlistHier = t
simVerilogLaiLmsiNetlisting = 'nil
verilogSimViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simVerilogAutoNetlisting = 't
simVerilogTestFixtureFlag = 'nil
simVerilogTestFixtureTemplate = "All"
simVerilogNetlistExplicit = 't
hnlVerilogTermSyncUp = 'nil
simVerilogFlattenBuses = 'nil
vtoolsUseUpperCaseFlag = 'nil
hnlVerilogCreatePM = 'nil
simVerilogTopLevelModuleName = ""
simHierarchyPrefix = ""
simNCVerilogHierPrefix = ""
verilogSimStopList = '("functional" "verilog" "symbol")
simVerilogPwrNetList = '("vddin_sub!" "vddout_sub!" "vddin!" "vddout!" "vddin_sub" "vddout_sub" "vddin" "vddout" "vddfx")
simVerilogGndNetList = '("vssfx!" "vss_sub!" "vssfx" "vss_sub")
vtoolsifForceReNetlisting = 'nil
simVerilogLibNames = '("stdcell_lib")
vlogifInternalTestFixtureFlag = 'nil
simVerilogBusJustificationStr = "U"
simVerilogTestFixtureTemplate = "All"
simVerilogDropPortRange = 't
simVerilogHandleUseLib = 'nil
simVerilogHandleAliasPort = 't
simVerilogPrintStimulusNameMappingTable = 'nil
simVerilogProcessNullPorts = 'nil
simVerilogIncrementalNetlistConfigList = 'nil
hnlVerilogNetlistStopCellImplicit = 'nil
simVerilogOverWriteSchTimeScale = 'nil
vlogifCompatibilityMode = "4.0"
simVerilogHandleSwitchRCData = 'nil
vlogifUseAssignsForAlias = 'nil
vlogifDeclareGlobalNetLocal = 'nil
vlogifSkipTimingInfo = 'nil
simVerilogEnableEscapeNameMapping = 't
simVerilogStopAfterCompilation = 't
simVerilogVhdlImport = 'nil
simVerilogTopCellCounter = 0
hnlSupportIterInst = 'nil

to be honest, i don't know what many of these options do. i probably have things defined i don't need. i literally just want it to netlist...don't need anything setup for simulation.

google searches showed that i need to set fnl* instead of hnl* in some places but nothing was really specific about the recipe for getting this flat netlisting to work properly.

wondering if anyone has experience with this and was able to get the flat verilog netlisting to work properly.

thanks!

Answer 1

finally was able to get a straight answer from cadence. the si netlist cannot create a flat verilog netlist unfortunately. many have requested this feature be added, but it is not being actively worked on.