How to edit and test a verilog netlist

Question

I've used a design compiler to produce a netlist for a simple serial adder.

I want to add a watermark to the design, which requires me to add a few gates and flip flops to the design.

How can I test the code after making edits (I'm not sure how to compile gate-level code, usually use ModelSim) to make sure it works, and how do I compile the new netlist.

P.S I am a noob, sry, any links to fundemental tutorials and stuff can help, thx :)

Answer 1

You can compile and simulate a netlist just like any other verilog design files. You will need to include the library files for the technology you synthesized for as part of your compilation filelist

Answer 2

Though the "coding styles" really differ bewteen your RTL .v and the gate-level netlist .v, there're no essential differences between them. A hierarchical HDL design is a design with nested modules. After synthesis, the AND gate inferred from & in your RTL becomes a newly created sub-module. Without the .v that defines such gate cells, your simulation tool doesn't know what functionality the AND gate has, and will report "Module 'AND' is not defined" errors. Such files are called standard library simulation models, and are mainly located inside frontend part of your library path. Try searching for "*.v" or "*.src", and incude them in your file list.