Number of active netlists exceeds limit

Question

Lately, I have been stuck with the same error from Vivado when I try to Synthesize my design:

[Common 17-70] Application Exception: Number of active netlists exceeds limit (255)

Does anybody know what this "limit" means? Is it a limitation of the software, or it refers to the capacity of the FPGA? Is there some way to avoid it, or do I have to change all my design in order to have fewer netlists?

Answer 1

I had the same problem. Restarting the vivado tool helped in my case.