I want to import a large combinatorial logic circuit created in Yosys into a directed graph in my own c++ routines with boost graph library, so I can experiment with my own algorithms. The logic has on the order of 10M gates, so it's goal to have performant code implementation.
It typically takes couple hours of crunching with yosys Berkeley abc to synthesize the circuit using and -g AND,OR,XOR . Exporting as verilog file takes some time also, and the file is huge (hundreds of megabytes)
My original plan was to simply read the verilog file and generate the directed graph from parsing the file strings. This is slow and requires alot of coding.
Is there an easier way? I was planing to use boost graph library just for fast easy graph traversal in algorithms.
Anyone have any example code or ideas of alternatives for efficient graph traversal? ..or fast importing of the big netlist into a graph structure?