I want to run a program on Rocket core and observe all the signals in corresponding registers in GTKwave (e.g. PC, register file, ALU registers and wires etc.)
However, the only I get (both in chipyard and rocket chip) is some strange list of wires in GTKwave, which I cannot relate to the core/tile.
I followed instructions at https://github.com/chipsalliance/rocket-chip for installations. I'm able to run:
make CONFIG = freechips.rocketchip.system.TinyConfig (I did DefaultConfig as well)
make verilog
etc.
Also I generate *.vcd files with
make run-debug CONFIG= freechips.rocketchip.system.TinyConfig
or specific file with hello word.
For each file there is corresponding *.out file with all executed instructions, so I naively think that I can run any of such generated *.vcd and see all the register states for all instructions.
However I get only strange wires
Elsewhere people demonstrate reasonable signals like this:
I observe at the last image TestBench group. I did test benches for modelsim with pure verilog written in Quartus. However for rocket chip framework and Verilator in particular, I think I can run any *.vcd file.
It looks for me the same approach used in theses page 26 with reasonable waves at page 27
Can somebody give me a hint, what is wrong with my approach?
As Jerry said on https://github.com/chipsalliance/rocket-chip/issues/2955, you can dig into the hierarchy to find the Rocket core and Rocket Tile. The wires you're seeing are the TestHarness. The DUT is the design under test beneath that and that contains the Rocket core.
The core should be under a path like:
ldut -> tile_prci_domain -> tile_reset_domain -> tile -> core