generate register delay for simulation in chisel

Question

When I am using Verilog, I would like to define a register like this:

reg [7:0] cnt;
always @ (posedge clk) begin
   cnt <= #1 cnt + 1;
end

Because of using #1, the register will change a little bit behind the clk posedge in the waveform, and it will be much clear in debugging.

I am wondering if I can do that in chisel3? Both in generating Verilog by Firrtl, and generating "vcd" waveform in iotester.

Answer 1

You cannot do this in Chisel. Chisel only supports a small, synthesizable subset of Verilog targeting synchronous, digital design. An important part of the ethos of Chisel is that simulation matches synthesis (you're simulating what you're taping out). While I totally see the use case in clearer waveforms, delays do so much more than that and aren't really appropriate for what Chisel is trying to accomplish.

It would be nice if waveform viewers themselves provided visual cues to help make this more clear rather than forcing the user to resort to delay tricks.