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20 TechQA 2024-03-23T18:17:45.927000Generating verilog file for rocket chip
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Asked by Srishti Sharma
In chisel6.2.0, how to use hex file to init memory and test it?
59 views
Asked by Fang Yongrui
With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?
37 views
Asked by FabienM
An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type
39 views
Asked by justin pan
Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?
42 views
Asked by FabienM
How to propagate a value from a Module upwards
34 views
Asked by hpmor123
Issues with creating an n-to-1 multiplexer in Chisel
67 views
Asked by Amadeus
a chisel problem about some value only read-only
39 views
Asked by peak
Expecting a SInt value from a Wire, in Chisel
97 views
Asked by Danish
How to implement the Gshare TAGE hybrid predictor combination on the RISC V BOOM core using Chisel
102 views
Asked by albie_01
Variable sized type in Chisel
35 views
Asked by G. S.
Adding a trivial bridge in FireSim
85 views
Asked by apaj
Using Chisel Submodule within another Module: Cannot assign variables to the io input
47 views
Asked by BurgerMan
Use def or val in Chisle to define some "const-macro" value?
41 views
Asked by Ning Ben
The problem with AyncFIFO with two clock sources written in Chisel 5.0
124 views
Asked by Ivean Don
sbt test does not work and all the tests fail
111 views
Asked by saras
How to export TileLink node to LazyModule's output and generate respective verilog file
37 views
Asked by armleo
Type Casting in Chisel: Converting UInt to Int
359 views
Asked by Asfiyan Shivani
How is the SiFive interactive L2 cache connected to the Chipyard SoC?
109 views
Asked by aoo