I am interested in building up a bridge in my firesim infrastructure. I posted already in the FireSim forum last week, but as there is little traction I am hoping cross-posting here won't make me troublemaker.
I've read the Bridge Walkthrough about the UARTBridge and just wanted to do a trivial example of adding another bridge with the same interface on the same bus - UART. Hence I copied all the files mentioned in the Walkthrough (why walkthrough is not a word?) and changed them into AdderBridge instead of UARTBridge, renaming the fields, as well as files themselves. I did that in forks of firesim and chipyard on my github account. All of it compiles successfully, but I don't see any trace of this AdderBridge in the elaboration phase and it doesn't show up in FireSim-const.h, as somebody suggested to check.
The thing I suspect is the culprit is how I added the address to the AdderBridge, here:
val ep = Module(new AdderBridge(UARTParams(address = 0x20040000)))
To be honest, I chose that number arbitrarily not having any idea how to actually pick the address. So, please, how should it be selected?
Also, if any other comment regarding the general concept of implementation - please, correct me wherever I am wrong.
If you have a working firesim environment, you could checkout the commits above and then in firesim you can do:
git submodule update --recursive
cd sim
make TARGET_CONFIG=FireSimRocketConfigAdder
This will compile successfully, however - without the AdderBridge. How to get AdderBridge in the emitted verilog?