Blocking the clock signal

Question

Let's say I need to find out that the BLOCK signal came earlier than the 5 clk signal. These signals are asynchronous to each other, so I can't use the classic construction as shown below.

always(posedge clk)
if(cnt==4 && !BLOCK)
flag<=1;
else 
flag<=0;
//The flag will be set to 1 only if the BLOCK signal does not arrive before 5 clk.

always(posedge clk)
cnt <= cnt + 1;

But I can block clk when the BLOCK signal arrives so that it stops clocking flag and the flag is not set to 1.

wire clk_flag = clk & !BLOCK;

always(posedge clk_flag)
if(cnt==4)
flag<=1;
else 
flag<=0;

//The flag will be set to 1 only if the BLOCK signal does not arrive before 5 clk

always(posedge clk)
cnt <= cnt + 1;

Is it acceptable to mix signals through "and" for clk in design?

Thanks.

Answer 1

Since BLOCK is asynchronous to clk, you need to use CDC for cnt signal. Or resync BLOCK to clk clock domain for first code construction.

Answer 2

there is a difference between two statements:

1. always@(posedge clk) will fire exactly at posedge clk
2. always@(posedge clk_flag) will fire either
   • at posedge clk if BLOCK is low
   • or at posedge !BLOCK when clk is high.

In other words, the second statement describes asynchronous behavior of BLOCK whether the first statement is synchronous.

So, you can have completely different timing for the flag.

Answer 3

1. The approach you've taken, using an AND operation between clk and !BLOCK to create a new clock signal clk_flag, is generally not recommended in digital design. Mixing clock and data signals through an AND gate can introduce metastability issues and is not a robust solution for handling asynchronous signals so it is important to use proper synchronization techniques such as, in this case,

   always @(posedge clk or posedge BLOCK) begin

   instead of

   always @(posedge clk_flag) begin.

2. If you are still thinking about blocking the clock signal, then there is another way to do it in FPGA i.e. to pass the clk through a buffer (BUFG in vivado) and connect the !block with the enable signal of the clock buffer. So after the block signal is high, the clock will be stopped by the buffer.

Hope that helps