Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?

Question

Recently I was learning 'Computer Organization and Design RISC-V' book by David A. Patterson, and was stuck by some questions. Why RISC-V 'J-immediate' put imm[11] in inst[20] instead of inst[24]?

Is it related with detailed circuit design, if so, Could someone offer reference link or better with more helpful explanation based on the specific circuit design?

I found valuable resources answering related questions about (S)B-immediate and also read some references like page 17 in official doc volume 1.

Answer 1

A short answer is it has to go somewhere, and the longer answer is that with that overall arrangement, three parts of the J-Type immediate then line up with other instructions formats.

The three parts of the J-Type immediate are:

• Imm[19:12], which lines up with UI-type format Imm[19:12] of its larger Imm[31:12]
• Imm[10:1], which lines up with the I-Type format Imm[10:1] of its larger Imm[11:0]
• Imm[20], which lines up with the sign bit for I-, UI-, S-, B- Types

That covers J-Type immediate Imm[20:12] and Imm[10:1], so what's left to encode/explain then is:

• Imm[0], however, since all branch addresses must be even it is simply take as zero rather than encoded in the instruction
• Imm[11], goes where it can!

As every other instruction field has a mapping, what's left in the instruction is Inst[20], so that is what Imm[11] is mapped to.  Despite being a somewhat odd position choice, it costs the hardware little overhead to move that bit to the right position while also putting a zero in the low bit position.

See also the two related answers here at this question: Why are RISC-V S-B and U-J instruction types encoded in this way?