Confused about instruction encoding supported by my core (ie. T1, T2, etc)
Having the STM32F0 series Cortex-M0 programming manual, I found that
https://www.st.com/resource/en/programming_manual/pm0215-stm32f0-series-cortexm0-programming-manual-stmicroelectronics.pdf
"The Cortex®-M0 processor implements the Arm®v6-M architecture, which is based on the 16-bit Thumb® instruction set and includes Thumb-2 technology."
Ok, so went for ARMv6M generic manual here https://developer.arm.com/documentation/ddi0419/c/ https://documentation-service.arm.com/static/5f8feef5f86e16515cdbf7e4?token=
And for example ADD (register) instruction has 2 flavors
Both of them are present in CPU?
Ok, so T1 updates flags and T2 doesn't, good to know :)
But later on in ARM manual says:
...If is omitted, this register is the same as and encoding T2 is preferred to encoding T1 if both are available.
So if both are available, how do I know if this is true for my STM32F? And in general, based on what criteria are these T1/T2 used by manufacturers? In STM32 programming manual I cannot find such info.
For NXP's LPC824 for example (also a Cortex M0) CPU exact type is missing, so guessing it's the same ARMv6M type.