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20 TechQA 2024-03-26T07:36:05.720000What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?
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Asked by Caroline Zou
x86_64 primary opcode byte categorization
93 views
Asked by Juliean
Breakdown MOV instruction on Intel 64 compatibility mode
130 views
Asked by Carlo C
How do I concatenate immediate value of type B RISC-V instruction?
312 views
Asked by TBG
Are these push r16 encodings correct under 64BIT mode?
63 views
Asked by YutakaAoki
Is the encoding "66| 48/ 0F 50 D8" in MASM for reg=rbx in "MOVMSKPD reg, xmm" correct?
165 views
Asked by YutakaAoki
What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?
119 views
Asked by YutakaAoki
Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?
254 views
Asked by An5Drama
How is data width determined for load/store instructions in Rocket Core?
44 views
Asked by JohnDoe
Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr
318 views
Asked by raff
Is "strb w0, [x2, w3, uxtw]" the same as "strb w0, [x2, w3, uxtw #0]"?
134 views
Asked by raff
Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?
419 views
Asked by Chris633
Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8
26 views
Asked by UPinar
Jump addressing from PC to a target
72 views
Asked by eswcs
Convert assembly instruction set to16-bit numbers
216 views
Asked by Quark
Opcode differences between MOV r/m32, imm32 and MOV r32, imm32
258 views
Asked by UPinar
getting an opcode? To perform jmp
237 views
Asked by Вили Били
Forcing a JMP rel32 (JMPQ)
276 views
Asked by Petr Skocik