TechQA.

Question

What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?

score 26 · Answer 1 · 2024-03-26T07:36:05.720000

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26

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What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?

26 views Asked by Caroline Zou At 26 March 2024 at 07:36

score 93 · Answer 2 · 2024-01-17T13:47:12.270000

x86_64 primary opcode byte categorization

93 views Asked by Juliean At 17 January 2024 at 13:47

score 130 · Answer 3 · 2023-12-04T10:32:10.487000

Breakdown MOV instruction on Intel 64 compatibility mode

130 views Asked by Carlo C At 04 December 2023 at 10:32

score 158 · Answer 4 · 2023-11-29T15:27:05.450000

Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example

158 views Asked by yo3hcv At 29 November 2023 at 15:27

score 312 · Answer 5 · 2023-10-10T03:10:56.083000

How do I concatenate immediate value of type B RISC-V instruction?

312 views Asked by TBG At 10 October 2023 at 03:10

score 63 · Answer 6 · 2023-07-29T10:33:20.140000

Are these push r16 encodings correct under 64BIT mode?

63 views Asked by YutakaAoki At 29 July 2023 at 10:33

score 165 · Answer 7 · 2023-07-23T09:27:07.717000

Is the encoding "66| 48/ 0F 50 D8" in MASM for reg=rbx in "MOVMSKPD reg, xmm" correct?

165 views Asked by YutakaAoki At 23 July 2023 at 09:27

score 119 · Answer 8 · 2023-07-15T04:44:25.740000

What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?

119 views Asked by YutakaAoki At 15 July 2023 at 04:44

score 254 · Answer 9 · 2023-05-27T13:42:34.290000

Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?

254 views Asked by An5Drama At 27 May 2023 at 13:42

score 44 · Answer 10 · 2023-05-25T17:51:11.277000

How is data width determined for load/store instructions in Rocket Core?

44 views Asked by JohnDoe At 25 May 2023 at 17:51

score 257 · Answer 11 · 2023-05-25T11:40:57.793000

Why does the opcode for MOV from a segment register not have its low bit set? It's not 8-bit operand-size, so the W bit should be set

257 views Asked by SmilyFace At 25 May 2023 at 11:40

score 318 · Answer 12 · 2023-04-24T10:49:26.137000

Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr

318 views Asked by raff At 24 April 2023 at 10:49

score 134 · Answer 13 · 2023-04-21T06:08:28.490000

Is "strb w0, [x2, w3, uxtw]" the same as "strb w0, [x2, w3, uxtw #0]"?

134 views Asked by raff At 21 April 2023 at 06:08

score 419 · Answer 14 · 2023-04-17T13:46:32.310000

Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?

419 views Asked by Chris633 At 17 April 2023 at 13:46

score 26 · Answer 15 · 2023-02-25T11:16:15.260000

Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8

26 views Asked by UPinar At 25 February 2023 at 11:16

score 72 · Answer 16 · 2023-02-21T17:56:11.617000

Jump addressing from PC to a target

72 views Asked by eswcs At 21 February 2023 at 17:56

score 216 · Answer 17 · 2023-01-31T20:53:48.613000

Convert assembly instruction set to16-bit numbers

216 views Asked by Quark At 31 January 2023 at 20:53

score 258 · Answer 18 · 2023-01-27T22:25:00.567000

Opcode differences between MOV r/m32, imm32 and MOV r32, imm32

258 views Asked by UPinar At 27 January 2023 at 22:25

score 237 · Answer 19 · 2023-01-15T21:22:32.597000

getting an opcode? To perform jmp

237 views Asked by Вили Били At 15 January 2023 at 21:22

score 276 · Answer 20 · 2022-12-12T12:50:13.723000

Forcing a JMP rel32 (JMPQ)

276 views Asked by Petr Skocik At 12 December 2022 at 12:50

TechQA.

List Question

What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?

x86_64 primary opcode byte categorization

Breakdown MOV instruction on Intel 64 compatibility mode

Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example

How do I concatenate immediate value of type B RISC-V instruction?

Are these push r16 encodings correct under 64BIT mode?

Is the encoding "66| 48/ 0F 50 D8" in MASM for reg=rbx in "MOVMSKPD reg, xmm" correct?

What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?

Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?

How is data width determined for load/store instructions in Rocket Core?

Why does the opcode for MOV from a segment register not have its low bit set? It's not 8-bit operand-size, so the W bit should be set

Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr

Is "strb w0, [x2, w3, uxtw]" the same as "strb w0, [x2, w3, uxtw #0]"?

Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?

Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8

Jump addressing from PC to a target

Convert assembly instruction set to16-bit numbers

Opcode differences between MOV r/m32, imm32 and MOV r32, imm32

getting an opcode? To perform jmp

Forcing a JMP rel32 (JMPQ)

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