Verilog FSM model shows wrong output

Question

I have been trying on the Verilog code for the FSM model which suits the case as below, but when I undergo the testing using ModelSim, the output (count) couldn't show the correct output I needed.

This is the simulation results I get:

The code i written is as below:

module fsmkey (
    input clock,
    input reset,
    input key,
    output reg [2:0] count);
    
parameter [2:0]   
    idle= 3'b000, 
     Key0 = 3'b000,
     Key1 = 3'b001,
    Key2 = 3'b010,
    Key3 = 3'b011,
    Key4 = 3'b100,
    Key5 = 3'b101,
    Key6 = 3'b110,
    Key7 = 3'b111;


    reg [1:0] state;
    reg [1:0] nxt_state;
    
always @ (posedge clock or posedge reset) 
begin
        if (reset) begin
            state = Key0;
            count = 3'b000;
            
        end
        else begin
            state = nxt_state;
            
        end
        
        case (state) 
        Key0: 
            begin
             if (count == 3'b000)
             begin
                count = 3'b000;
                nxt_state = Key0;
             end
             end
             
        Key1: 
            begin
             if (count == 3'b001)
             begin
                count = 3'b000;
                nxt_state = Key1;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key1;
                end
             end
            
        Key2: 
            begin
             if (count == 3'b010)
             begin
                count = 3'b000;
                nxt_state = Key2;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key2;
                end
             end
        
        Key3: 
            begin
             if (count == 3'b011)
             begin
                count = 3'b000;
                nxt_state = Key3;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key3;
                end
             end
             
        Key4: 
            begin
             if (count == 3'b100)
             begin
                count = 3'b000;
                nxt_state = Key4;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key4;
                end
             end
        
        Key5: 
            begin
             if (count == 3'b101)
             begin
                count = 3'b000;
                nxt_state = Key5;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key5;
                end
             end
             
        Key6: 
            begin
             if (count == 3'b110)
             begin
                count = 3'b000;
                nxt_state = Key6;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key6;
                end
             end
             
        Key7: 
            begin
             if (count == 3'b111)
             begin
                count = 3'b000;
                nxt_state = Key7;
             end
                else
                begin
                count = count + 1;
                nxt_state = Key7;
                end
             end

            default: nxt_state = idle;
            endcase
        end

endmodule 

Below are the testbench:

module fsmkey_testbench();

    reg clock = 0;
    reg reset = 1;
    reg key;
    wire [2:0] count;

    // Instantiate the fsmkey module
    fsmkey dut (
        .clock(clock),
        .reset(reset),
        .key(key),
        .count(count)
    );

    // Clock generation
    always #5 clock = ~clock; // Toggle clock every 5 time units

    initial begin
        // Reset the unit
        reset = 0;

        // Simulate key presses
        key = 3'b000;
        #10 key = 3'b001; // Press Key0
        #10 key = 0;

        key = 3'b001;
        #10 key = 3'b001; // Press Key1
        #10 key = 0;

        key = 3'b000;
        #10 key = 3'b001; // Press Key0
        #10 key = 0;

        key = 3'b001;
        #10 key = 3'b001; // Press Key1
        #10 key = 0;

        // Continue simulating key presses for other keys as needed...

        $stop; // Stop simulation
    end

    // Display count value
    always @(posedge clock) begin
        $display("Count = %b", count);
    end

endmodule

I couldnt find the part where is affecting my simulation. The results should be following the FSM model as above, with the count showing the result

Answer 1

You see count = x (unknown) because you did not reset the design properly in the testbench. You initialized reset to 1 properly at time 0, but you then immediately set it to 0 also at time 0. You need to add some delay. Change:

    reset = 0;

to:

    #20 reset = 0;

This causes count to become known (0).

However, count remains 0 due to a bug in your FSM. You reset the FSM to state Key0, but then you provide no way of leaving that state. Typically, you would make an assignment to nxt_state to a state other than Key0 inside the case statement.

Also, the key input to the design module is unused. Your block diagram shows it as a 3-bit signal, but you declare it as a 1-bit signal.