Data Hazard(True Dependencies) in MIPS

Question

I1:LW R1, 0(R4) ; R1 ← address (0+R4)
I2:ADDI R2, R1, #8 ; R2 ← R1+8
I3:MULT R3, R1, R1 ; R3 ← R1*R1
I4:SW R3, 4(R2) ; address(4+R2) ← R3 

In the MIPS code above, in an solution sheet, a true dependency is marked as I3->I4 for R3. From my understanding true dependencies are RAW(read after write) hazards or flow hazards. I am pretty sure though that this is an write after write hazard and therefore not a true dependency. Am I correct to say this?

Answer 1

write after write hazard

No, this is not a write after write hazard.  While I4 appears to be a write operation — and relative to memory it is indeed a write operation — from a micro architectural point of view, i.e. inside the processor alone where the pipeline stages and registers are located and operate, a store instruction has two source operands and no register target.

So, R3 is read by I4 after being written by I3.  (In other words, the store instruction requires the value of R3, as the value fed to perform the memory store; R3's value is fed to the data memory, along with the address of where to store, and size, here 4).  Thus, this is a read after write hazard.