I'm studying RISC-V (32-bit) computer architechture and I'm having a hard time understanding this type of data hazard. Suppose that we have instructions like this:
or x4, x3, x4
bne x4, x4, error (not taken)
addi x2, x0, 1060
sw x4, 0(x2)
Suppose that the format of sw instruction is sw rs2, rs1(12-bit immediate). At the sw instruction, we get the value of rs2 (x4) in the decoding stage, but the value of x4 changes by the "or x4, x3, x4" instruction. As far as I know, the value of the register is updated at the clock right after the writeback stage. So at the decoding stage of the "sw" instruction, the data at the register file is not updated. Therefore a data hazard happens.
But I learned that data hazard only happens between ID/EX stage and EX/MEM, MEM/WB stage, not after the WB stage. How do we deal with this data hazard? Or, am I misunderstanding something? Any help is appreciated!