There is a RISCV (5 stages pipeline 32-bits) If we supose there is no hazard unit nor forwarding support, so I have to add nop instructions.
If the branch policy is Branch never taken, so we have to add nops after j loop, but also have to add nops after bge instructions? Because in the last iteration of the loop, there is a misprediction, so the processor needs these flush supposing we could have some instructions after getting out of the loop that can depend of the result of the instructions after bge (slli in this case).
I'm trying to understand how works a 5 stage pipeline riscv processor